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ruanhaishen
Nodemcu Firmware
Commits
1f759353
Commit
1f759353
authored
Nov 18, 2017
by
devsaurus
Browse files
remove u8g
parent
fd745e09
Changes
102
Hide whitespace changes
Inline
Side-by-side
app/u8glib/u8g_dev_flipdisc_2x7.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_flipdisc.c
1-Bit (BW) Driver for flip disc matrix
2x 7 pixel height
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 28
#define HEIGHT 14
#define PAGE_HEIGHT 14
/*
Write data to the flip disc matrix.
This procedure must be implemented by the user.
Arguments:
id: Id for the matrix. Currently always 0.
page: A page has a height of 14 pixel. For a matrix with HEIGHT == 14 this will be always 0
width: The width of the flip disc matrix. Always equal to WIDTH
row1: first data line (7 pixel per byte)
row2: first data line (7 pixel per byte)
*/
void
writeFlipDiscMatrix
(
uint8_t
id
,
uint8_t
page
,
uint8_t
width
,
uint8_t
*
row1
,
uint8_t
*
row2
);
void
(
*
u8g_write_flip_disc_matrix
)(
uint8_t
id
,
uint8_t
page
,
uint8_t
width
,
uint8_t
*
row1
,
uint8_t
*
row2
);
void
u8g_SetFlipDiscCallback
(
u8g_t
*
u8g
,
void
(
*
cb
)(
uint8_t
id
,
uint8_t
page
,
uint8_t
width
,
uint8_t
*
row1
,
uint8_t
*
row2
))
{
u8g_write_flip_disc_matrix
=
cb
;
}
uint8_t
u8g_dev_flipdisc_2x7_bw_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
/* current page: pb->p.page */
/* ptr to the buffer: pb->buf */
(
*
u8g_write_flip_disc_matrix
)(
0
,
pb
->
p
.
page
,
WIDTH
,
pb
->
buf
,
(
uint8_t
*
)(
pb
->
buf
)
+
WIDTH
);
}
break
;
case
U8G_DEV_MSG_CONTRAST
:
return
1
;
}
return
u8g_dev_pb14v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
uint8_t
u8g_dev_flipdisc_2x7_bw_buf
[
WIDTH
*
2
]
U8G_NOCOMMON
;
u8g_pb_t
u8g_dev_flipdisc_2x7_bw_pb
=
{
{
16
,
HEIGHT
,
0
,
0
,
0
},
WIDTH
,
u8g_dev_flipdisc_2x7_bw_buf
};
u8g_dev_t
u8g_dev_flipdisc_2x7
=
{
u8g_dev_flipdisc_2x7_bw_fn
,
&
u8g_dev_flipdisc_2x7_bw_pb
,
u8g_com_null_fn
};
app/u8glib/u8g_dev_gprof.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_gprof.c
Device for performance measurement with gprof.
Does not write any data, but uses a buffer.
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 64
#define PAGE_HEIGHT 8
uint8_t
u8g_dev_gprof_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
);
uint8_t
u8g_pb_dev_gprof_buf
[
WIDTH
];
u8g_pb_t
u8g_pb_dev_gprof
=
{
{
PAGE_HEIGHT
,
HEIGHT
,
0
,
0
,
0
},
WIDTH
,
u8g_pb_dev_gprof_buf
};
u8g_dev_t
u8g_dev_gprof
=
{
u8g_dev_gprof_fn
,
&
u8g_pb_dev_gprof
,
NULL
};
uint8_t
u8g_dev_gprof_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_FIRST
:
u8g_pb_Clear
(
pb
);
u8g_page_First
(
&
(
pb
->
p
));
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
/*
{
uint8_t i, j;
uint8_t page_height;
page_height = pb->p.page_y1;
page_height -= pb->p.page_y0;
page_height++;
for( j = 0; j < page_height; j++ )
{
printf("%02d ", j);
for( i = 0; i < WIDTH; i++ )
{
if ( (u8g_pb_dev_stdout_buf[i] & (1<<j)) != 0 )
printf("#");
else
printf(".");
}
printf("\n");
}
}
*/
if
(
u8g_page_Next
(
&
(
pb
->
p
))
==
0
)
{
//printf("\n");
return
0
;
}
u8g_pb_Clear
(
pb
);
break
;
#ifdef U8G_DEV_MSG_IS_BBX_INTERSECTION
case
U8G_DEV_MSG_IS_BBX_INTERSECTION
:
{
u8g_dev_arg_bbx_t
*
bbx
=
(
u8g_dev_arg_bbx_t
*
)
arg
;
u8g_uint_t
x2
,
y2
;
y2
=
bbx
->
y
;
y2
+=
bbx
->
h
;
y2
--
;
if
(
u8g_pb_IsYIntersection
(
pb
,
bbx
->
y
,
y2
)
==
0
)
return
0
;
/* maybe this one can be skiped... probability is very high to have an intersection, so it would be ok to always return 1 */
x2
=
bbx
->
x
;
x2
+=
bbx
->
w
;
x2
--
;
if
(
u8g_pb_IsXIntersection
(
pb
,
bbx
->
x
,
x2
)
==
0
)
return
0
;
}
return
1
;
#endif
case
U8G_DEV_MSG_GET_PAGE_BOX
:
u8g_pb_GetPageBox
(
pb
,
(
u8g_box_t
*
)
arg
);
break
;
case
U8G_DEV_MSG_SET_COLOR_ENTRY
:
break
;
case
U8G_DEV_MSG_SET_XY_CB
:
break
;
}
return
u8g_dev_pb8v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
app/u8glib/u8g_dev_ht1632.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_ht1632.c
1-Bit (BW) Driver for HT1632 controller
Universal 8bit Graphics Library
Copyright (c) 2013, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
U8G_PIN_NONE can be used as argument
uint8_t u8g_InitSPI(u8g_t *u8g, u8g_dev_t *dev, uint8_t sck, uint8_t mosi, uint8_t cs, uint8_t a0, uint8_t reset)
{
...
u8g->pin_list[U8G_PI_SCK] = sck;
u8g->pin_list[U8G_PI_MOSI] = mosi;
u8g->pin_list[U8G_PI_CS] = cs;
u8g->pin_list[U8G_PI_A0] = a0;
u8g->pin_list[U8G_PI_RESET] = reset;
mapping
#define DATA_PIN --> U8G_PI_MOSI
#define WR_PIN --> U8G_PI_SCK
#define CS_PIN --> U8G_PI_CS
U8G_PI_A0 --> not used
U8G_PI_RESET --> not used
Usage:
u8g_InitSPI(&u8g, &u8g_dev_ht1632_24x16, WR_PIN, DATA_IN, CS_PIN, U8G_PIN_NONE, U8G_PIN_NONE)
*/
#include "u8g.h"
#define WIDTH 24
#define HEIGHT 16
#define PAGE_HEIGHT 16
/* http://forum.arduino.cc/index.php?topic=168537.0 */
#define HT1632_CMD_SYSDIS 0x00 // CMD= 0000-0000-x Turn off oscil
#define HT1632_CMD_SYSON 0x01 // CMD= 0000-0001-x Enable system oscil
#define HT1632_CMD_LEDOFF 0x02 // CMD= 0000-0010-x LED duty cycle gen off
#define HT1632_CMD_LEDON 0x03 // CMD= 0000-0011-x LEDs ON
#define HT1632_CMD_BLOFF 0x08 // CMD= 0000-1000-x Blink OFF
#define HT1632_CMD_BLON 0x09 // CMD= 0000-1001-x Blink On
#define HT1632_CMD_SLVMD 0x10 // CMD= 0001-00xx-x Slave Mode
#define HT1632_CMD_MSTMD 0x14 // CMD= 0001-01xx-x Master Mode
#define HT1632_CMD_RCCLK 0x18 // CMD= 0001-10xx-x Use on-chip clock
#define HT1632_CMD_EXTCLK 0x1C // CMD= 0001-11xx-x Use external clock
#define HT1632_CMD_COMS00 0x20 // CMD= 0010-ABxx-x commons options
#define HT1632_CMD_COMS01 0x24 // CMD= 0010-ABxx-x commons options
#define HT1632_CMD_COMS10 0x28 // CMD= 0010-ABxx-x commons options
#define HT1632_CMD_COMS11 0x2C // P-MOS OUTPUT AND 16COMMON OPTION
#define HT1632_CMD_PWM 0xA0 // CMD= 101x-PPPP-x PWM duty cycle
#define HT1632_ID_CMD 4
/* ID = 100 - Commands */
#define HT1632_ID_RD 6
/* ID = 110 - Read RAM */
#define HT1632_ID_WR 5
/* ID = 101 - Write RAM */
#define HT1632_ID_LEN 3 // IDs are 3 bits
#define HT1632_CMD_LEN 8 // CMDs are 8 bits
#define HT1632_DATA_LEN 8 // Data are 4*2 bits
#define HT1632_ADDR_LEN 7 // Address are 7 bits
#if defined(ARDUINO)
#if ARDUINO < 100
#include <WProgram.h>
#else
#include <Arduino.h>
#endif
//#define WR_PIN 3
//#define DATA_PIN 2
//#define CS_PIN 4
void
ht1632_write_data_MSB
(
u8g_t
*
u8g
,
uint8_t
cnt
,
uint8_t
data
,
uint8_t
extra
)
{
int8_t
i
;
uint8_t
data_pin
=
u8g
->
pin_list
[
U8G_PI_MOSI
];
uint8_t
wr_pin
=
u8g
->
pin_list
[
U8G_PI_SCK
];
for
(
i
=
cnt
-
1
;
i
>=
0
;
i
--
)
{
if
((
data
>>
i
)
&
1
)
{
digitalWrite
(
data_pin
,
HIGH
);
}
else
{
digitalWrite
(
data_pin
,
LOW
);
}
digitalWrite
(
wr_pin
,
LOW
);
u8g_MicroDelay
();
digitalWrite
(
wr_pin
,
HIGH
);
u8g_MicroDelay
();
}
// Send an extra bit
if
(
extra
)
{
digitalWrite
(
data_pin
,
HIGH
);
digitalWrite
(
wr_pin
,
LOW
);
u8g_MicroDelay
();
digitalWrite
(
wr_pin
,
HIGH
);
u8g_MicroDelay
();
}
}
void
ht1632_write_data
(
u8g_t
*
u8g
,
uint8_t
cnt
,
uint8_t
data
)
{
uint8_t
i
;
uint8_t
data_pin
=
u8g
->
pin_list
[
U8G_PI_MOSI
];
uint8_t
wr_pin
=
u8g
->
pin_list
[
U8G_PI_SCK
];
for
(
i
=
0
;
i
<
cnt
;
i
++
)
{
if
((
data
>>
i
)
&
1
)
{
digitalWrite
(
data_pin
,
HIGH
);
}
else
{
digitalWrite
(
data_pin
,
LOW
);
}
digitalWrite
(
wr_pin
,
LOW
);
u8g_MicroDelay
();
digitalWrite
(
wr_pin
,
HIGH
);
u8g_MicroDelay
();
}
}
void
ht1632_init
(
u8g_t
*
u8g
)
{
//uint8_t i;
uint8_t
data_pin
=
u8g
->
pin_list
[
U8G_PI_MOSI
];
uint8_t
wr_pin
=
u8g
->
pin_list
[
U8G_PI_SCK
];
uint8_t
cs_pin
=
u8g
->
pin_list
[
U8G_PI_CS
];
pinMode
(
data_pin
,
OUTPUT
);
pinMode
(
wr_pin
,
OUTPUT
);
pinMode
(
cs_pin
,
OUTPUT
);
digitalWrite
(
data_pin
,
HIGH
);
digitalWrite
(
wr_pin
,
HIGH
);
digitalWrite
(
cs_pin
,
HIGH
);
digitalWrite
(
cs_pin
,
LOW
);
/* init display once after startup */
ht1632_write_data_MSB
(
u8g
,
3
,
HT1632_ID_CMD
,
false
);
// IDs are 3 bits
ht1632_write_data_MSB
(
u8g
,
8
,
HT1632_CMD_SYSDIS
,
true
);
// 8 bits
ht1632_write_data_MSB
(
u8g
,
8
,
HT1632_CMD_SYSON
,
true
);
// 8 bits
ht1632_write_data_MSB
(
u8g
,
8
,
HT1632_CMD_COMS11
,
true
);
// 8 bits
ht1632_write_data_MSB
(
u8g
,
8
,
HT1632_CMD_LEDON
,
true
);
// 8 bits
ht1632_write_data_MSB
(
u8g
,
8
,
HT1632_CMD_BLOFF
,
true
);
// 8 bits
ht1632_write_data_MSB
(
u8g
,
8
,
HT1632_CMD_PWM
+
15
,
true
);
// 8 bits
digitalWrite
(
cs_pin
,
HIGH
);
/* removed following (debug) code */
/*
digitalWrite(cs_pin, LOW);
ht1632_write_data_MSB(u8g, 3, HT1632_ID_WR, false); // Send "write to display" command
ht1632_write_data_MSB(u8g, 7, 0, false);
for(i = 0; i<48; ++i)
{
ht1632_write_data(u8g, 8, 0xFF);
}
digitalWrite(cs_pin, HIGH);
*/
}
/*
page: 0=data contain lines 0..16, 1=data contain lines 16..32 (a 24x16 display will only have page 0)
cnt: width of the display
data: pointer to a buffer with 2*cnt bytes.
*/
void
ht1632_transfer_data
(
u8g_t
*
u8g
,
uint8_t
page
,
uint8_t
cnt
,
uint8_t
*
data
)
{
uint8_t
addr
;
uint8_t
cs_pin
=
u8g
->
pin_list
[
U8G_PI_CS
];
/* send data to the ht1632 */
digitalWrite
(
cs_pin
,
LOW
);
ht1632_write_data_MSB
(
u8g
,
3
,
HT1632_ID_WR
,
false
);
// Send "write to display" command
ht1632_write_data_MSB
(
u8g
,
7
,
page
*
2
*
cnt
,
false
);
// Operating in progressive addressing mode
for
(
addr
=
0
;
addr
<
cnt
;
addr
++
)
{
ht1632_write_data
(
u8g
,
8
,
data
[
addr
]);
ht1632_write_data
(
u8g
,
8
,
data
[
addr
+
cnt
]);
}
digitalWrite
(
cs_pin
,
HIGH
);
}
/* value is between 0...15 */
void
ht1632_set_contrast
(
u8g_t
*
u8g
,
uint8_t
value
)
{
uint8_t
cs_pin
=
u8g
->
pin_list
[
U8G_PI_CS
];
digitalWrite
(
cs_pin
,
LOW
);
ht1632_write_data_MSB
(
u8g
,
3
,
HT1632_ID_CMD
,
false
);
ht1632_write_data_MSB
(
u8g
,
8
,
HT1632_CMD_PWM
+
value
,
false
);
digitalWrite
(
cs_pin
,
HIGH
);
}
#else
void
ht1632_init
(
u8g_t
*
u8g
)
{
}
void
ht1632_transfer_data
(
u8g_t
*
u8g
,
uint8_t
page
,
uint8_t
cnt
,
uint8_t
*
data
)
{
}
void
ht1632_set_contrast
(
u8g_t
*
u8g
,
uint8_t
value
)
{
}
#endif
/* ARDUINO */
uint8_t
u8g_dev_ht1632_24x16_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
ht1632_init
(
u8g
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
/* current page: pb->p.page */
/* ptr to the buffer: pb->buf */
ht1632_transfer_data
(
u8g
,
pb
->
p
.
page
,
WIDTH
,
pb
->
buf
);
}
break
;
case
U8G_DEV_MSG_CONTRAST
:
/* values passed to SetContrast() are between 0 and 255, scale down to 0...15 */
ht1632_set_contrast
(
u8g
,
(
*
(
uint8_t
*
)
arg
)
>>
4
);
return
1
;
}
return
u8g_dev_pb16v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
uint8_t
u8g_dev_ht1632_24x16_buf
[
WIDTH
*
2
]
U8G_NOCOMMON
;
u8g_pb_t
u8g_dev_ht1632_24x16_pb
=
{
{
16
,
HEIGHT
,
0
,
0
,
0
},
WIDTH
,
u8g_dev_ht1632_24x16_buf
};
u8g_dev_t
u8g_dev_ht1632_24x16
=
{
u8g_dev_ht1632_24x16_fn
,
&
u8g_dev_ht1632_24x16_pb
,
u8g_com_null_fn
};
app/u8glib/u8g_dev_ili9325d_320x240.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_ili9325d_320x240.c
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Color format
Red: 5 Bit
Green: 6 Bit
Blue: 5 Bit
*/
#include "u8g.h"
#define WIDTH 240
#if defined(U8G_16BIT)
#define HEIGHT 320
#else
/* if the user tries to compile the 8Bit version of the lib, then restrict the height to something which fits to 8Bit */
#define HEIGHT 240
#endif
#define PAGE_HEIGHT 4
/*
reference board for this device:
http://iteadstudio.com/store/index.php?main_page=product_info&cPath=57_58&products_id=55
documentation:
http://iteadstudio.com/Downloadfile/ITDB02_material.rar
datasheet
http://www.newhavendisplay.com/app_notes/ILI9325D.pdf
other libs
http://henningkarlsen.com/electronics/library.php
init sequence
http://code.google.com/p/itdb02/, ITDB02.cpp, iteadstudio.com
*/
static
const
uint8_t
u8g_dev_ili9325d_320x240_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_RST
(
15
),
/* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_RST
(
15
),
/* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_CS
(
1
),
/* enable chip */
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
//U8G_ESC_ADR(0), 0x000, 0x0E5, /* only used for none D version: set SRAM internal timing */
//U8G_ESC_ADR(1), 0x078, 0x0f0,
U8G_ESC_ADR
(
0
),
0x000
,
0x001
,
/* Driver Output Control, bits 8 & 10 */
U8G_ESC_ADR
(
1
),
0x001
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x002
,
/* LCD Driving Wave Control, bit 9: Set line inversion */
U8G_ESC_ADR
(
1
),
0x002
,
0x000
,
/* ITDB02 none D verion: 0x007, 0x000 */
U8G_ESC_ADR
(
0
),
0x000
,
0x003
,
/* Entry Mode, GRAM write direction and BGR=1 */
U8G_ESC_ADR
(
1
),
0x010
,
0x030
,
U8G_ESC_ADR
(
0
),
0x000
,
0x004
,
/* Resize register */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x008
,
/* Display Control 2: set the back porch and front porch */
U8G_ESC_ADR
(
1
),
0x002
,
0x007
,
U8G_ESC_ADR
(
0
),
0x000
,
0x009
,
/* Display Control 3 */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x00a
,
/* Display Control 4: FMARK */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x00c
,
/* RGB Display Interface Control 1 */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x00d
,
/* Frame Maker Position */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x00f
,
/* RGB Display Interface Control 2 */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x010
,
/* Power Control 1: SAP, BT[3:0], AP, DSTB, SLP, STB */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x011
,
/* Power Control 2: DC1[2:0], DC0[2:0], VC[2:0] */
U8G_ESC_ADR
(
1
),
0x000
,
0x007
,
U8G_ESC_ADR
(
0
),
0x000
,
0x012
,
/* Power Control 3: VREG1OUT voltage */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x013
,
/* Power Control 4: VDV[4:0] for VCOM amplitude */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x007
,
/* Display Control 1: Operate, but do not display */
U8G_ESC_ADR
(
1
),
0x000
,
0x001
,
U8G_ESC_DLY
(
100
),
/* delay 100 ms */
/* ITDB02 none D verion: 50ms */
U8G_ESC_DLY
(
100
),
/* delay 100 ms */
U8G_ESC_ADR
(
0
),
0x000
,
0x010
,
/* Power Control 1: SAP, BT[3:0], AP, DSTB, SLP, STB */
U8G_ESC_ADR
(
1
),
0x016
,
0x090
,
/* ITDB02 none D verion: 0x010, 0x090 */
U8G_ESC_ADR
(
0
),
0x000
,
0x011
,
/* Power Control 2: SAP, BT[3:0], AP, DSTB, SLP, STB */
U8G_ESC_ADR
(
1
),
0x002
,
0x027
,
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_ADR
(
0
),
0x000
,
0x012
,
/* Power Control 3: VCI: External, VCI*1.80 */
U8G_ESC_ADR
(
1
),
0x000
,
0x00d
,
/* ITDB02 none D verion: 0x000, 0x01f */
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_ADR
(
0
),
0x000
,
0x013
,
/* Power Control 4: VDV[4:0] for VCOM amplitude */
U8G_ESC_ADR
(
1
),
0x012
,
0x000
,
/* ITDB02 none D verion: 0x015, 0x000 */
U8G_ESC_ADR
(
0
),
0x000
,
0x029
,
/* Power Control 7 */
U8G_ESC_ADR
(
1
),
0x000
,
0x00a
,
/* ITDB02 none D verion: 0x000, 0x027 */
U8G_ESC_ADR
(
0
),
0x000
,
0x02b
,
/* Frame Rate: 83 */
U8G_ESC_ADR
(
1
),
0x000
,
0x00d
,
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_ADR
(
0
),
0x000
,
0x020
,
/* Horizontal GRAM Address Set */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x021
,
/* Vertical GRAM Address Set */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
/* gamma control */
U8G_ESC_ADR
(
0
),
0x000
,
0x030
,
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x031
,
U8G_ESC_ADR
(
1
),
0x004
,
0x004
,
U8G_ESC_ADR
(
0
),
0x000
,
0x032
,
U8G_ESC_ADR
(
1
),
0x000
,
0x003
,
U8G_ESC_ADR
(
0
),
0x000
,
0x035
,
U8G_ESC_ADR
(
1
),
0x004
,
0x005
,
U8G_ESC_ADR
(
0
),
0x000
,
0x036
,
U8G_ESC_ADR
(
1
),
0x008
,
0x008
,
U8G_ESC_ADR
(
0
),
0x000
,
0x037
,
U8G_ESC_ADR
(
1
),
0x004
,
0x007
,
U8G_ESC_ADR
(
0
),
0x000
,
0x038
,
U8G_ESC_ADR
(
1
),
0x003
,
0x003
,
U8G_ESC_ADR
(
0
),
0x000
,
0x039
,
U8G_ESC_ADR
(
1
),
0x007
,
0x007
,
U8G_ESC_ADR
(
0
),
0x000
,
0x03c
,
U8G_ESC_ADR
(
1
),
0x005
,
0x004
,
U8G_ESC_ADR
(
0
),
0x000
,
0x03d
,
U8G_ESC_ADR
(
1
),
0x008
,
0x008
,
U8G_ESC_ADR
(
0
),
0x000
,
0x050
,
/* Horizontal GRAM Start Address */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x051
,
/* Horizontal GRAM End Address: 239 */
U8G_ESC_ADR
(
1
),
0x000
,
0x0EF
,
U8G_ESC_ADR
(
0
),
0x000
,
0x052
,
/* Vertical GRAM Start Address */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x053
,
/* Vertical GRAM End Address: 319 */
U8G_ESC_ADR
(
1
),
0x001
,
0x03F
,
U8G_ESC_ADR
(
0
),
0x000
,
0x060
,
/* Driver Output Control 2 */
U8G_ESC_ADR
(
1
),
0x0a7
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x061
,
/* Base Image Display Control: NDL,VLE, REV */
U8G_ESC_ADR
(
1
),
0x000
,
0x001
,
U8G_ESC_ADR
(
0
),
0x000
,
0x06a
,
/* Vertical Scroll Control */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x080
,
/* Partial Image 1 Display Position */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x081
,
/* Partial Image 1 RAM Start Address */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x082
,
/* Partial Image 1 RAM End Address */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x083
,
/* Partial Image 2 Display Position */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x084
,
/* Partial Image 2 RAM Start Address */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x085
,
/* Partial Image 2 RAM End Address */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x090
,
/* Panel Interface Control 1 */
U8G_ESC_ADR
(
1
),
0x000
,
0x010
,
U8G_ESC_ADR
(
0
),
0x000
,
0x092
,
/* Panel Interface Control 2 */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
/* 0x006, 0x000 */
U8G_ESC_ADR
(
0
),
0x000
,
0x007
,
/* Display Control 1: Operate, display ON */
U8G_ESC_ADR
(
1
),
0x001
,
0x033
,
U8G_ESC_DLY
(
10
),
/* delay 10 ms */
/* write test pattern */
U8G_ESC_ADR
(
0
),
0x000
,
0x020
,
/* Horizontal GRAM Address Set */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x021
,
/* Vertical GRAM Address Set */
U8G_ESC_ADR
(
1
),
0x000
,
0x010
,
U8G_ESC_ADR
(
0
),
0x000
,
0x022
,
/* Write Data to GRAM */
U8G_ESC_ADR
(
1
),
0x0fe
,
0x0fe
,
0x000
,
0x000
,
0x0fe
,
0x0fe
,
0x000
,
0x000
,
0x0fe
,
0x0fe
,
0x000
,
0x000
,
0x0fe
,
0x0fe
,
0x000
,
0x000
,
0x0fe
,
0x0fe
,
0x000
,
0x000
,
0x0fe
,
0x0fe
,
0x000
,
0x000
,
0x0fe
,
0x0fe
,
0x000
,
0x000
,
0x0fe
,
0x0fe
,
0x000
,
0x000
,
0x0fe
,
0x0fe
,
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ili9325d_320x240_page_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
1
),
/* enable chip */
U8G_ESC_ADR
(
0
),
0x000
,
0x020
,
/* Horizontal GRAM Address Set */
U8G_ESC_ADR
(
1
),
0x000
,
0x000
,
U8G_ESC_ADR
(
0
),
0x000
,
0x021
,
/* Vertical GRAM Address Set */
U8G_ESC_ADR
(
1
),
U8G_ESC_END
/* end of sequence */
};
/* convert the internal RGB 332 to 65K high byte */
static
uint8_t
u8g_dev_ili9325d_get_65K_high_byte
(
uint8_t
color
)
{
uint8_t
h
;
h
=
color
;
h
&=
0x0e0
;
h
|=
h
>>
3
;
h
&=
0x0f8
;
color
>>=
2
;
color
&=
7
;
h
|=
color
;
return
h
;
}
/* convert the internal RGB 332 to 65K high byte */
static
uint8_t
u8g_dev_ili9325d_get_65K_low_byte
(
uint8_t
color
)
{
uint8_t
l
;
l
=
color
;
l
<<=
3
;
color
&=
3
;
color
<<=
1
;
l
|=
color
;
return
l
;
}
uint8_t
u8g_dev_ili9325d_320x240_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_50NS
);
//for(;;)
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ili9325d_320x240_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
uint8_t
i
;
uint16_t
y
,
j
;
uint8_t
*
ptr
;
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
y
=
pb
->
p
.
page_y0
;
ptr
=
pb
->
buf
;
for
(
i
=
0
;
i
<
pb
->
p
.
page_height
;
i
++
)
{
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ili9325d_320x240_page_seq
);
u8g_WriteByte
(
u8g
,
dev
,
y
>>
8
);
/* display ram (cursor) address high byte */
u8g_WriteByte
(
u8g
,
dev
,
y
&
255
);
/* display ram (cursor) address low byte */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* cmd mode */
u8g_WriteByte
(
u8g
,
dev
,
0
);
u8g_WriteByte
(
u8g
,
dev
,
0x022
);
/* start gram data */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
for
(
j
=
0
;
j
<
pb
->
width
;
j
++
)
{
u8g_WriteByte
(
u8g
,
dev
,
u8g_dev_ili9325d_get_65K_high_byte
(
*
ptr
)
);
u8g_WriteByte
(
u8g
,
dev
,
u8g_dev_ili9325d_get_65K_low_byte
(
*
ptr
)
);
ptr
++
;
}
y
++
;
}
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
}
return
u8g_dev_pb8h8_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
uint8_t
u8g_ili9325d_320x240_8h8_buf
[
WIDTH
*
PAGE_HEIGHT
]
U8G_NOCOMMON
;
u8g_pb_t
u8g_ili9325d_320x240_8h8_pb
U8G_NOCOMMON
=
{
{
PAGE_HEIGHT
,
HEIGHT
,
0
,
0
,
0
},
WIDTH
,
u8g_ili9325d_320x240_8h8_buf
};
u8g_dev_t
u8g_dev_ili9325d_320x240_8bit
U8G_NOCOMMON
=
{
u8g_dev_ili9325d_320x240_fn
,
&
u8g_ili9325d_320x240_8h8_pb
,
u8g_com_arduino_port_d_wr_fn
};
//u8g_dev_t u8g_dev_ili9325d_320x240_8bit = { u8g_dev_ili9325d_320x240_fn, &u8g_ili9325d_320x240_8h8_pb, u8g_com_arduino_parallel_fn };
//U8G_PB_DEV(u8g_dev_ili9325d_320x240_8bit, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ili9325d_320x240_fn, U8G_COM_PARALLEL);
app/u8glib/u8g_dev_ks0108_128x64.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_ks0108_128x64.c
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ADDRESS = 0 (Command Mode)
0x03f Display On
0x0c0 Start Display at line 0
0x040 | y write to y address (y:0..63)
0x0b8 | x write to page [0..7]
u8g_Init8Bit(u8g, dev, d0, d1, d2, d3, d4, d5, d6, d7, en, cs1, cs2, di, rw, reset)
u8g_Init8Bit(u8g, dev, 8, 9, 10, 11, 4, 5, 6, 7, 18, 14, 15, 17, 16, U8G_PIN_NONE)
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 64
#define PAGE_HEIGHT 8
static
const
uint8_t
u8g_dev_ks0108_128x64_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip 1 */
0x03f
,
/* display on */
0x0c0
,
/* start at line 0 */
U8G_ESC_DLY
(
20
),
/* delay 20 ms */
U8G_ESC_CS
(
2
),
/* enable chip 2 */
0x03f
,
/* display on */
0x0c0
,
/* start at line 0 */
U8G_ESC_DLY
(
20
),
/* delay 20 ms */
U8G_ESC_CS
(
0
),
/* disable all chips */
U8G_ESC_END
/* end of sequence */
};
uint8_t
u8g_dev_ks0108_128x64_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_NONE
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ks0108_128x64_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* command mode */
u8g_SetChipSelect
(
u8g
,
dev
,
2
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b8
|
pb
->
p
.
page
);
/* select current page (KS0108b) */
u8g_WriteByte
(
u8g
,
dev
,
0x040
);
/* set address 0 */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
64
,
pb
->
buf
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* command mode */
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b8
|
pb
->
p
.
page
);
/* select current page (KS0108b) */
u8g_WriteByte
(
u8g
,
dev
,
0x040
);
/* set address 0 */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
64
,
64
+
(
uint8_t
*
)
pb
->
buf
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
}
return
u8g_dev_pb8v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
U8G_PB_DEV
(
u8g_dev_ks0108_128x64
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ks0108_128x64_fn
,
U8G_COM_PARALLEL
);
U8G_PB_DEV
(
u8g_dev_ks0108_128x64_fast
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ks0108_128x64_fn
,
U8G_COM_FAST_PARALLEL
);
app/u8glib/u8g_dev_lc7981_160x80.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_lc7981_160x80.c
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 160
#define HEIGHT 80
#define PAGE_HEIGHT 8
/*
code ideas:
https://github.com/vsergeev/embedded-drivers/tree/master/avr-lc7981
data sheets:
http://www.lcd-module.de/eng/pdf/zubehoer/lc7981.pdf
http://www.lcd-module.de/pdf/grafik/w160-6.pdf
*/
static
const
uint8_t
u8g_dev_lc7981_160x80_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
1
),
/* instruction mode */
U8G_ESC_RST
(
15
),
/* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
U8G_ESC_CS
(
1
),
/* enable chip */
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x000
,
/* mode register */
U8G_ESC_ADR
(
0
),
/* data mode */
0x032
,
/* display on (bit 5), master mode on (bit 4), graphics mode on (bit 1)*/
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x001
,
/* character/bits per pixel pitch */
U8G_ESC_ADR
(
0
),
/* data mode */
0x007
,
/* 8 bits per pixel */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x002
,
/* number of chars/byte width of the screen */
U8G_ESC_ADR
(
0
),
/* data mode */
WIDTH
/
8
-
1
,
/* 8 bits per pixel */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x003
,
/* time division */
U8G_ESC_ADR
(
0
),
/* data mode */
0x050
,
/* Oct 2015: Changed from 7f to 50 (1/80 duty cycle) */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x008
,
/* display start low */
U8G_ESC_ADR
(
0
),
/* data mode */
0x000
,
/* */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x009
,
/* display start high */
U8G_ESC_ADR
(
0
),
/* data mode */
0x000
,
/* */
U8G_ESC_DLY
(
10
),
/* delay 10 ms */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
uint8_t
u8g_dev_lc7981_160x80_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_NONE
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_lc7981_160x80_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
uint8_t
y
,
i
;
uint16_t
disp_ram_adr
;
uint8_t
*
ptr
;
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
y
=
pb
->
p
.
page_y0
;
ptr
=
pb
->
buf
;
disp_ram_adr
=
WIDTH
/
8
;
disp_ram_adr
*=
y
;
for
(
i
=
0
;
i
<
8
;
i
++
)
{
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_WriteByte
(
u8g
,
dev
,
0x00a
);
/* display ram (cursor) address low byte */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* data mode */
u8g_WriteByte
(
u8g
,
dev
,
disp_ram_adr
&
0x0ff
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_WriteByte
(
u8g
,
dev
,
0x00b
);
/* display ram (cursor) address hight byte */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* data mode */
u8g_WriteByte
(
u8g
,
dev
,
disp_ram_adr
>>
8
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_WriteByte
(
u8g
,
dev
,
0x00c
);
/* write data */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
WIDTH
/
8
,
ptr
);
ptr
+=
WIDTH
/
8
;
disp_ram_adr
+=
WIDTH
/
8
;
}
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
}
return
u8g_dev_pb8h1f_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
U8G_PB_DEV
(
u8g_dev_lc7981_160x80_8bit
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_lc7981_160x80_fn
,
U8G_COM_FAST_PARALLEL
);
app/u8glib/u8g_dev_lc7981_240x128.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_lc7981_240x128.c
Hitachi Display SP14N002
Universal 8bit Graphics Library
Copyright (c) 2012, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 240
#define HEIGHT 128
#define PAGE_HEIGHT 8
/*
http://www.mark-products.com/graphics.htm#240x128%20Pixel%20Format
*/
static
const
uint8_t
u8g_dev_lc7981_240x128_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
1
),
/* instruction mode */
U8G_ESC_RST
(
15
),
/* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
U8G_ESC_CS
(
1
),
/* enable chip */
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x000
,
/* mode register */
U8G_ESC_ADR
(
0
),
/* data mode */
0x032
,
/* display on (bit 5), master mode on (bit 4), graphics mode on (bit 1)*/
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x001
,
/* character/bits per pixel pitch */
U8G_ESC_ADR
(
0
),
/* data mode */
0x007
,
/* 8 bits per pixel */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x002
,
/* number of chars/byte width of the screen */
U8G_ESC_ADR
(
0
),
/* data mode */
WIDTH
/
8
-
1
,
/* 8 bits per pixel */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x003
,
/* time division */
U8G_ESC_ADR
(
0
),
/* data mode */
0x07f
,
/* */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x008
,
/* display start low */
U8G_ESC_ADR
(
0
),
/* data mode */
0x000
,
/* */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x009
,
/* display start high */
U8G_ESC_ADR
(
0
),
/* data mode */
0x000
,
/* */
U8G_ESC_DLY
(
10
),
/* delay 10 ms */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
uint8_t
u8g_dev_lc7981_240x128_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_NONE
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_lc7981_240x128_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
uint8_t
y
,
i
;
uint16_t
disp_ram_adr
;
uint8_t
*
ptr
;
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
y
=
pb
->
p
.
page_y0
;
ptr
=
pb
->
buf
;
disp_ram_adr
=
WIDTH
/
8
;
disp_ram_adr
*=
y
;
for
(
i
=
0
;
i
<
8
;
i
++
)
{
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_WriteByte
(
u8g
,
dev
,
0x00a
);
/* display ram (cursor) address low byte */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* data mode */
u8g_WriteByte
(
u8g
,
dev
,
disp_ram_adr
&
0x0ff
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_WriteByte
(
u8g
,
dev
,
0x00b
);
/* display ram (cursor) address hight byte */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* data mode */
u8g_WriteByte
(
u8g
,
dev
,
disp_ram_adr
>>
8
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_WriteByte
(
u8g
,
dev
,
0x00c
);
/* write data */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
WIDTH
/
8
,
ptr
);
ptr
+=
WIDTH
/
8
;
disp_ram_adr
+=
WIDTH
/
8
;
}
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
}
return
u8g_dev_pb8h1f_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
U8G_PB_DEV
(
u8g_dev_lc7981_240x128_8bit
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_lc7981_240x128_fn
,
U8G_COM_FAST_PARALLEL
);
app/u8glib/u8g_dev_lc7981_240x64.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_lc7981_240x64.c
Tested with Nan Ya LM_J6_003_
Universal 8bit Graphics Library
Copyright (c) 2012, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 240
#define HEIGHT 64
#define PAGE_HEIGHT 8
/*
http://www.mark-products.com/graphics.htm#240x64%20Pixel%20Format
*/
static
const
uint8_t
u8g_dev_lc7981_240x64_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
1
),
/* instruction mode */
U8G_ESC_RST
(
15
),
/* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
U8G_ESC_CS
(
1
),
/* enable chip */
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x000
,
/* mode register */
U8G_ESC_ADR
(
0
),
/* data mode */
0x032
,
/* display on (bit 5), master mode on (bit 4), graphics mode on (bit 1)*/
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x001
,
/* character/bits per pixel pitch */
U8G_ESC_ADR
(
0
),
/* data mode */
0x007
,
/* 8 bits per pixel */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x002
,
/* number of chars/byte width of the screen */
U8G_ESC_ADR
(
0
),
/* data mode */
WIDTH
/
8
-
1
,
/* 8 bits per pixel */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x003
,
/* time division */
U8G_ESC_ADR
(
0
),
/* data mode */
0x07f
,
/* */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x008
,
/* display start low */
U8G_ESC_ADR
(
0
),
/* data mode */
0x000
,
/* */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x009
,
/* display start high */
U8G_ESC_ADR
(
0
),
/* data mode */
0x000
,
/* */
U8G_ESC_DLY
(
10
),
/* delay 10 ms */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
uint8_t
u8g_dev_lc7981_240x64_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_NONE
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_lc7981_240x64_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
uint8_t
y
,
i
;
uint16_t
disp_ram_adr
;
uint8_t
*
ptr
;
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
y
=
pb
->
p
.
page_y0
;
ptr
=
pb
->
buf
;
disp_ram_adr
=
WIDTH
/
8
;
disp_ram_adr
*=
y
;
for
(
i
=
0
;
i
<
8
;
i
++
)
{
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_WriteByte
(
u8g
,
dev
,
0x00a
);
/* display ram (cursor) address low byte */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* data mode */
u8g_WriteByte
(
u8g
,
dev
,
disp_ram_adr
&
0x0ff
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_WriteByte
(
u8g
,
dev
,
0x00b
);
/* display ram (cursor) address hight byte */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* data mode */
u8g_WriteByte
(
u8g
,
dev
,
disp_ram_adr
>>
8
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_WriteByte
(
u8g
,
dev
,
0x00c
);
/* write data */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
WIDTH
/
8
,
ptr
);
ptr
+=
WIDTH
/
8
;
disp_ram_adr
+=
WIDTH
/
8
;
}
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
}
return
u8g_dev_pb8h1f_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
U8G_PB_DEV
(
u8g_dev_lc7981_240x64_8bit
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_lc7981_240x64_fn
,
U8G_COM_FAST_PARALLEL
);
app/u8glib/u8g_dev_lc7981_320x64.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_lc7981_320x64.c
Note: Requires 16 bit mode (Must be enabled in u8g.h)
Tested with Varitronix MGLS32064-03.pdf
Universal 8bit Graphics Library
Copyright (c) 2012, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#ifdef U8G_16BIT
#define WIDTH 320
#else
#define WIDTH 240
#endif
#define HEIGHT 64
#define PAGE_HEIGHT 8
/*
http://www.gaw.ru/pdf/lcd/lcm/Varitronix/graf/MGLS32064-03.pdf
*/
static
const
uint8_t
u8g_dev_lc7981_320x64_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
1
),
/* instruction mode */
U8G_ESC_RST
(
15
),
/* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
U8G_ESC_CS
(
1
),
/* enable chip */
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x000
,
/* mode register */
U8G_ESC_ADR
(
0
),
/* data mode */
0x032
,
/* display on (bit 5), master mode on (bit 4), graphics mode on (bit 1)*/
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x001
,
/* character/bits per pixel pitch */
U8G_ESC_ADR
(
0
),
/* data mode */
0x007
,
/* 8 bits per pixel */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x002
,
/* number of chars/byte width of the screen */
U8G_ESC_ADR
(
0
),
/* data mode */
WIDTH
/
8
-
1
,
/* 8 bits per pixel */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x003
,
/* time division */
U8G_ESC_ADR
(
0
),
/* data mode */
0x07f
,
/* */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x008
,
/* display start low */
U8G_ESC_ADR
(
0
),
/* data mode */
0x000
,
/* */
U8G_ESC_ADR
(
1
),
/* instruction mode */
0x009
,
/* display start high */
U8G_ESC_ADR
(
0
),
/* data mode */
0x000
,
/* */
U8G_ESC_DLY
(
10
),
/* delay 10 ms */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
uint8_t
u8g_dev_lc7981_320x64_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_NONE
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_lc7981_320x64_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
uint8_t
y
,
i
;
uint16_t
disp_ram_adr
;
uint8_t
*
ptr
;
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
y
=
pb
->
p
.
page_y0
;
ptr
=
pb
->
buf
;
disp_ram_adr
=
WIDTH
/
8
;
disp_ram_adr
*=
y
;
for
(
i
=
0
;
i
<
8
;
i
++
)
{
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_WriteByte
(
u8g
,
dev
,
0x00a
);
/* display ram (cursor) address low byte */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* data mode */
u8g_WriteByte
(
u8g
,
dev
,
disp_ram_adr
&
0x0ff
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_WriteByte
(
u8g
,
dev
,
0x00b
);
/* display ram (cursor) address hight byte */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* data mode */
u8g_WriteByte
(
u8g
,
dev
,
disp_ram_adr
>>
8
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* cmd mode */
u8g_WriteByte
(
u8g
,
dev
,
0x00c
);
/* write data */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
WIDTH
/
8
,
ptr
);
ptr
+=
WIDTH
/
8
;
disp_ram_adr
+=
WIDTH
/
8
;
}
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
}
return
u8g_dev_pb8h1f_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
U8G_PB_DEV
(
u8g_dev_lc7981_320x64_8bit
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_lc7981_320x64_fn
,
U8G_COM_FAST_PARALLEL
);
app/u8glib/u8g_dev_ld7032_60x32.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_ld7032_60x32.c
60x32 OLED display
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
/* define width as 64, so that it is a multiple of 8 */
#define WIDTH 64
#define HEIGHT 32
#define PAGE_HEIGHT 8
static
const
uint8_t
u8g_dev_ld7032_60x32_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_DLY
(
1
),
/* delay 1 ms */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x002
,
/* Dot Matrix Display ON/OFF */
U8G_ESC_ADR
(
1
),
/* data mode */
0x001
,
/* ON */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x014
,
/* Dot Matrix Display Stand-by ON/OFF */
U8G_ESC_ADR
(
1
),
/* data mode */
0x000
,
/* ON */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x01a
,
/* Dot Matrix Frame Rate */
U8G_ESC_ADR
(
1
),
/* data mode */
0x004
,
/* special value for this OLED from manual */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x01d
,
/* Graphics Memory Writing Direction */
U8G_ESC_ADR
(
1
),
/* data mode */
0x000
,
/* reset default (right down, horizontal) */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x009
,
/* Display Direction */
U8G_ESC_ADR
(
1
),
/* data mode */
0x000
,
/* reset default (x,y: min --> max) */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x030
,
/* Display Size X */
U8G_ESC_ADR
(
1
),
/* data mode */
0x000
,
/* Column Start Output */
0x03b
,
/* Column End Output */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x032
,
/* Display Size Y */
U8G_ESC_ADR
(
1
),
/* data mode */
0x000
,
/* Row Start Output */
0x01f
,
/* Row End Output */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x010
,
/* Peak Pulse Width Set */
U8G_ESC_ADR
(
1
),
/* data mode */
0x000
,
/* 0 SCLK */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x016
,
/* Peak Pulse Delay Set */
U8G_ESC_ADR
(
1
),
/* data mode */
0x000
,
/* 0 SCLK */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x012
,
/* Dot Matrix Current Level Set */
U8G_ESC_ADR
(
1
),
/* data mode */
0x050
,
/* 0x050 * 1 uA = 80 uA */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x018
,
/* Pre-Charge Pulse Width */
U8G_ESC_ADR
(
1
),
/* data mode */
0x003
,
/* 3 SCLK */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x044
,
/* Pre-Charge Mode */
U8G_ESC_ADR
(
1
),
/* data mode */
0x002
,
/* Every Time */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x048
,
/* Row overlap timing */
U8G_ESC_ADR
(
1
),
/* data mode */
0x003
,
/* Pre-Charge + Peak Delay + Peak boot Timing */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x03f
,
/* VCC_R_SEL */
U8G_ESC_ADR
(
1
),
/* data mode */
0x011
,
/* ??? */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x03d
,
/* VSS selection */
U8G_ESC_ADR
(
1
),
/* data mode */
0x000
,
/* 2.8V */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x002
,
/* Dot Matrix Display ON/OFF */
U8G_ESC_ADR
(
1
),
/* data mode */
0x001
,
/* ON */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x008
,
/* write data */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
/* use box commands to set start adr */
static
const
uint8_t
u8g_dev_ld7032_60x32_data_start
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x034
,
/* box x start */
U8G_ESC_ADR
(
1
),
/* data mode */
0x000
,
/* 0 */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x035
,
/* box x end */
U8G_ESC_ADR
(
1
),
/* data mode */
0x007
,
/* */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x037
,
/* box y end */
U8G_ESC_ADR
(
1
),
/* data mode */
0x01f
,
/* */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x036
,
/* box y start */
U8G_ESC_ADR
(
1
),
/* data mode */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ld7032_60x32_sleep_on
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
/* ... */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ld7032_60x32_sleep_off
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
/* ... */
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
uint8_t
u8g_dev_ld7032_60x32_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_400NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ld7032_60x32_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ld7032_60x32_data_start
);
u8g_WriteByte
(
u8g
,
dev
,
pb
->
p
.
page_y0
);
/* y start */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x008
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
if
(
u8g_pb_WriteBuffer
(
pb
,
u8g
,
dev
)
==
0
)
return
0
;
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
case
U8G_DEV_MSG_CONTRAST
:
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x081
);
u8g_WriteByte
(
u8g
,
dev
,
(
*
(
uint8_t
*
)
arg
)
>>
2
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
return
1
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ld7032_60x32_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ld7032_60x32_sleep_off
);
return
1
;
}
return
u8g_dev_pb8h1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
U8G_PB_DEV
(
u8g_dev_ld7032_60x32_sw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ld7032_60x32_fn
,
U8G_COM_SW_SPI
);
U8G_PB_DEV
(
u8g_dev_ld7032_60x32_hw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ld7032_60x32_fn
,
U8G_COM_HW_SPI
);
U8G_PB_DEV
(
u8g_dev_ld7032_60x32_parallel
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ld7032_60x32_fn
,
U8G_COM_PARALLEL
);
U8G_PB_DEV
(
u8g_dev_ld7032_60x32_hw_usart_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ld7032_60x32_fn
,
U8G_COM_HW_USART_SPI
);
app/u8glib/u8g_dev_null.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_null.c
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
uint8_t
u8g_dev_null
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_SET_8PIXEL
:
/* most often used command */
break
;
case
U8G_DEV_MSG_SET_PIXEL
:
break
;
case
U8G_DEV_MSG_INIT
:
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_FIRST
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
break
;
#ifdef U8G_DEV_MSG_IS_BBX_INTERSECTION
case
U8G_DEV_MSG_IS_BBX_INTERSECTION
:
return
1
;
#endif
case
U8G_DEV_MSG_GET_PAGE_BOX
:
break
;
case
U8G_DEV_MSG_SET_COLOR_ENTRY
:
break
;
case
U8G_DEV_MSG_SET_XY_CB
:
break
;
}
return
1
;
}
app/u8glib/u8g_dev_pcd8544_84x48.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_pcd8544_84x48.c
Display: Nokia 84x48
Status: Tested with PCF8812 Display
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 84
#define HEIGHT 48
#define PAGE_HEIGHT 8
static
const
uint8_t
u8g_dev_pcd8544_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip */
0x021
,
/* activate chip (PD=0), horizontal increment (V=0), enter extended command set (H=1) */
0x006
,
/* temp. control: b10 = 2 */
0x013
,
/* bias system 1:48 */
0x0c0
,
/* medium Vop */
0x020
,
/* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */
0x00c
,
/* display on, normal operation */
U8G_ESC_DLY
(
100
),
/* delay 100 ms */
0x020
,
/* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */
0x00d
,
/* display on, invert */
U8G_ESC_DLY
(
100
),
/* delay 100 ms */
U8G_ESC_DLY
(
100
),
/* delay 100 ms */
0x020
,
/* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */
0x00c
,
/* display on, normal */
U8G_ESC_DLY
(
100
),
/* delay 100 ms */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_pcd8544_sleep_on
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x020
,
/* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */
0x00c
,
/* display on, normal */
U8G_ESC_CS
(
0
),
/* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_pcd8544_sleep_off
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x020
,
/* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */
0x008
,
/* display blank */
0x024
,
/* power down (PD=1), horizontal increment (V=0), enter normal command set (H=0) */
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_CS
(
0
),
/* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END
/* end of sequence */
};
uint8_t
u8g_dev_pcd8544_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_400NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_pcd8544_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* command mode */
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_WriteByte
(
u8g
,
dev
,
0x020
);
/* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */
u8g_WriteByte
(
u8g
,
dev
,
0x080
);
/* set X address */
u8g_WriteByte
(
u8g
,
dev
,
0x040
|
pb
->
p
.
page
);
/* set Y address */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
if
(
u8g_pb_WriteBuffer
(
pb
,
u8g
,
dev
)
==
0
)
return
0
;
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
case
U8G_DEV_MSG_CONTRAST
:
/* the contrast adjustment does not work, needs to be analysed */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_WriteByte
(
u8g
,
dev
,
0x021
);
/* command mode, extended function set */
u8g_WriteByte
(
u8g
,
dev
,
0x080
|
(
(
*
(
uint8_t
*
)
arg
)
>>
1
)
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
return
1
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_pcd8544_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_pcd8544_sleep_off
);
return
1
;
}
return
u8g_dev_pb8v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
U8G_PB_DEV
(
u8g_dev_pcd8544_84x48_sw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_pcd8544_fn
,
U8G_COM_SW_SPI
);
U8G_PB_DEV
(
u8g_dev_pcd8544_84x48_hw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_pcd8544_fn
,
U8G_COM_HW_SPI
);
app/u8glib/u8g_dev_pcf8812_96x65.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_pcf8812_96x65.c
Display: Nokia 96x65
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
om6206 comaptible to pcf8812 ?
Status: Tested
Display Controller Seen in
LPH7366 (9 pins, 84x48) PCD8544 Nokia 5110 / 5120 / 5130 / 5160 / 6110 / 6150
LPH7677 (8 pins, 84x48) PCD8544 Nokia 3210
LPH7779 (8 pins, 84x48) PCD8544 Nokia 3310 / 3315 / 3330 / 3110, also 3410?
??? PCD8544 Nokia 5110 / 6110
LPH7690 ? (96x65) PCF8455/OM6202 Nokia 3410
LPH7690 ? (96x65?) SED1565/S1D15605 Nokia 7110 / 3510?
LPH7690 ??? Nokia 6210
*/
#include "u8g.h"
#define WIDTH 96
#define HEIGHT 65
#define PAGE_HEIGHT 8
static
const
uint8_t
u8g_dev_pcf8812_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip */
0x021
,
/* activate chip (PD=0), horizontal increment (V=0), enter extended command set (H=1) */
0x006
,
/* temp. control: b10 = 2 */
0x013
,
/* bias system 1:48 */
0x080
|
0x040
,
/* medium Vop */
0x020
,
/* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */
0x00c
,
/* display on, normal operation */
U8G_ESC_DLY
(
100
),
/* delay 100 ms */
0x020
,
/* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */
0x00d
,
/* display on, invert */
U8G_ESC_DLY
(
100
),
/* delay 100 ms */
U8G_ESC_DLY
(
100
),
/* delay 100 ms */
0x020
,
/* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */
0x00c
,
/* display on, normal */
U8G_ESC_DLY
(
100
),
/* delay 100 ms */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
uint8_t
u8g_dev_pcf8812_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_400NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_pcf8812_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* command mode */
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_WriteByte
(
u8g
,
dev
,
0x020
);
/* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */
u8g_WriteByte
(
u8g
,
dev
,
0x080
);
/* set X address */
u8g_WriteByte
(
u8g
,
dev
,
0x040
|
pb
->
p
.
page
);
/* set Y address */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
if
(
u8g_pb_WriteBuffer
(
pb
,
u8g
,
dev
)
==
0
)
return
0
;
/* mirrored output, not tested*/
/*
{
uint8_t i = pb->width;
while( i > 0 )
{
i--;
u8g_WriteByte(u8g, dev, ((unsigned char *)pb->buf)[i] );
}
}
*/
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
case
U8G_DEV_MSG_CONTRAST
:
/* the contrast adjustment does not work, needs to be analysed */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_WriteByte
(
u8g
,
dev
,
0x021
);
/* command mode, extended function set */
u8g_WriteByte
(
u8g
,
dev
,
0x080
|
(
(
*
(
uint8_t
*
)
arg
)
>>
1
)
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
return
1
;
}
return
u8g_dev_pb8v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
/* u8g_com_arduino_sw_spi_fn does not work, too fast??? */
U8G_PB_DEV
(
u8g_dev_pcf8812_96x65_sw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_pcf8812_fn
,
U8G_COM_SW_SPI
);
U8G_PB_DEV
(
u8g_dev_pcf8812_96x65_hw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_pcf8812_fn
,
U8G_COM_HW_SPI
);
app/u8glib/u8g_dev_sbn1661_122x32.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_sbn1661_122x32.c
WG12232 display with 2xSBN1661 / SED1520 controller (122x32 display)
At the moment only available in the Arduino Environment
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 122
#define HEIGHT 32
#define PAGE_HEIGHT 8
static
const
uint8_t
u8g_dev_sbn1661_122x32_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
15
),
/* do reset low pulse with (15*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip 1 */
0x0af
,
/* display on */
0x0c0
,
/* display start at line 0 */
0x0a0
,
/* a0: ADC forward, a1: ADC reverse */
0x0a9
,
/* a8: 1/16, a9: 1/32 duty */
U8G_ESC_CS
(
2
),
/* enable chip 2 */
0x0af
,
/* display on */
0x0c0
,
/* display start at line 0 */
0x0a0
,
/* a0: ADC forward, a1: ADC reverse */
0x0a9
,
/* a8: 1/16, a9: 1/32 duty */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
uint8_t
u8g_dev_sbn1661_122x32_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_NONE
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_sbn1661_122x32_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* command mode */
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b8
|
pb
->
p
.
page
);
/* select current page (SBN1661/SED1520) */
u8g_WriteByte
(
u8g
,
dev
,
0x000
);
/* set X address */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
WIDTH
/
2
,
pb
->
buf
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* command mode */
u8g_SetChipSelect
(
u8g
,
dev
,
2
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b8
|
pb
->
p
.
page
);
/* select current page (SBN1661/SED1520) */
u8g_WriteByte
(
u8g
,
dev
,
0x000
);
/* set X address */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
WIDTH
/
2
,
WIDTH
/
2
+
(
uint8_t
*
)
pb
->
buf
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
case
U8G_DEV_MSG_CONTRAST
:
break
;
}
return
u8g_dev_pb8v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
/* u8g_com_arduino_sw_spi_fn does not work, too fast??? */
U8G_PB_DEV
(
u8g_dev_sbn1661_122x32
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_sbn1661_122x32_fn
,
u8g_com_arduino_no_en_parallel_fn
);
app/u8glib/u8g_dev_ssd1306_128x32.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_ssd1306_128x32.c
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 Feb 2013: Fixed, Issue 147
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 32
#define PAGE_HEIGHT 8
/* init sequence adafruit 128x32 OLED (NOT TESTED) */
static
const
uint8_t
u8g_dev_ssd1306_128x32_adafruit1_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0ae
,
/* display off, sleep mode */
0x0d5
,
0x080
,
/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
0x0a8
,
0x03f
,
/* */
0x0d3
,
0x000
,
/* */
0x040
,
/* start line */
0x08d
,
0x010
,
/* [1] charge pump setting (p62): 0x014 enable, 0x010 disable */
0x020
,
0x000
,
/* */
0x0a1
,
/* segment remap a0/a1*/
0x0c8
,
/* c0: scan dir normal, c8: reverse */
0x0da
,
0x012
,
/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
0x081
,
0x09f
,
/* [1] set contrast control */
0x0d9
,
0x022
,
/* [1] pre-charge period 0x022/f1*/
0x0db
,
0x040
,
/* vcomh deselect level */
0x02e
,
/* 2012-05-27: Deactivate scroll */
0x0a4
,
/* output ram to display */
0x0a6
,
/* none inverted normal display mode */
0x0af
,
/* display on */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
/* init sequence adafruit 128x32 OLED (NOT TESTED) */
static
const
uint8_t
u8g_dev_ssd1306_128x32_adafruit2_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0ae
,
/* display off, sleep mode */
0x0d5
,
0x080
,
/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
0x0a8
,
0x03f
,
/* */
0x0d3
,
0x000
,
/* */
0x040
,
/* start line */
0x08d
,
0x014
,
/* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
0x020
,
0x000
,
/* */
0x0a1
,
/* segment remap a0/a1*/
0x0c8
,
/* c0: scan dir normal, c8: reverse */
0x0da
,
0x012
,
/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
0x081
,
0x0cf
,
/* [2] set contrast control */
0x0d9
,
0x0f1
,
/* [2] pre-charge period 0x022/f1*/
0x0db
,
0x040
,
/* vcomh deselect level */
0x02e
,
/* 2012-05-27: Deactivate scroll */
0x0a4
,
/* output ram to display */
0x0a6
,
/* none inverted normal display mode */
0x0af
,
/* display on */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
/* init sequence adafruit 128x32 OLED (TESTED - WORKING 23.02.13), like adafruit3, but with page addressing mode */
static
const
uint8_t
u8g_dev_ssd1306_128x32_adafruit3_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0ae
,
/* display off, sleep mode */
0x0d5
,
0x080
,
/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
0x0a8
,
0x01f
,
/* Feb 23, 2013: 128x32 OLED: 0x01f, 128x32 OLED 0x03f */
0x0d3
,
0x000
,
/* */
0x040
,
/* start line */
0x08d
,
0x014
,
/* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
0x020
,
0x002
,
/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), Feb 23, 2013: 128x32 OLED: 0x002, 128x32 OLED 0x012 */
0x0a1
,
/* segment remap a0/a1*/
0x0c8
,
/* c0: scan dir normal, c8: reverse */
0x0da
,
0x002
,
/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
0x081
,
0x0cf
,
/* [2] set contrast control */
0x0d9
,
0x0f1
,
/* [2] pre-charge period 0x022/f1*/
0x0db
,
0x040
,
/* vcomh deselect level */
0x02e
,
/* 2012-05-27: Deactivate scroll */
0x0a4
,
/* output ram to display */
0x0a6
,
/* none inverted normal display mode */
0x0af
,
/* display on */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
/* init sequence Univision datasheet (NOT TESTED) */
static
const
uint8_t
u8g_dev_ssd1306_128x32_univision_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0ae
,
/* display off, sleep mode */
0x0d5
,
0x080
,
/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
0x0a8
,
0x03f
,
/* multiplex ratio */
0x0d3
,
0x000
,
/* display offset */
0x040
,
/* start line */
0x08d
,
0x010
,
/* charge pump setting (p62): 0x014 enable, 0x010 disable */
0x0a1
,
/* segment remap a0/a1*/
0x0c8
,
/* c0: scan dir normal, c8: reverse */
0x0da
,
0x012
,
/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
0x081
,
0x09f
,
/* set contrast control */
0x0d9
,
0x022
,
/* pre-charge period */
0x0db
,
0x040
,
/* vcomh deselect level */
0x022
,
0x000
,
/* page addressing mode WRONG: 3 byte cmd! */
0x0a4
,
/* output ram to display */
0x0a6
,
/* none inverted normal display mode */
0x0af
,
/* display on */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
/* select one init sequence here */
//define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_univision_init_seq
//define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_adafruit1_init_seq
//define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_adafruit2_init_seq
#define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_adafruit3_init_seq
static
const
uint8_t
u8g_dev_ssd1306_128x32_data_start
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x010
,
/* set upper 4 bit of the col adr. to 0 */
0x000
,
/* set lower 4 bit of the col adr. to 4 */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ssd13xx_sleep_on
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0ae
,
/* display off */
U8G_ESC_CS
(
0
),
/* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ssd13xx_sleep_off
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0af
,
/* display on */
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_CS
(
0
),
/* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END
/* end of sequence */
};
uint8_t
u8g_dev_ssd1306_128x32_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_300NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_128x32_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_128x32_data_start
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b0
|
pb
->
p
.
page
);
/* select current page (SSD1306) */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
if
(
u8g_pb_WriteBuffer
(
pb
,
u8g
,
dev
)
==
0
)
return
0
;
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
case
U8G_DEV_MSG_CONTRAST
:
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x081
);
u8g_WriteByte
(
u8g
,
dev
,
(
*
(
uint8_t
*
)
arg
)
);
/* 11 Jul 2015: fixed contrast calculation */
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
return
1
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_off
);
return
1
;
}
return
u8g_dev_pb8v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
uint8_t
u8g_dev_ssd1306_128x32_2x_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_300NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_128x32_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_128x32_data_start
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b0
|
(
pb
->
p
.
page
*
2
));
/* select current page (SSD1306) */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
pb
->
width
,
pb
->
buf
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_128x32_data_start
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b0
|
(
pb
->
p
.
page
*
2
+
1
));
/* select current page (SSD1306) */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
pb
->
width
,
(
uint8_t
*
)(
pb
->
buf
)
+
pb
->
width
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
case
U8G_DEV_MSG_CONTRAST
:
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x081
);
u8g_WriteByte
(
u8g
,
dev
,
(
*
(
uint8_t
*
)
arg
)
);
/* 11 Jul 2015: fixed contrast calculation */
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
return
1
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_off
);
return
1
;
}
return
u8g_dev_pb16v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
U8G_PB_DEV
(
u8g_dev_ssd1306_128x32_sw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1306_128x32_fn
,
U8G_COM_SW_SPI
);
U8G_PB_DEV
(
u8g_dev_ssd1306_128x32_hw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1306_128x32_fn
,
U8G_COM_HW_SPI
);
U8G_PB_DEV
(
u8g_dev_ssd1306_128x32_i2c
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1306_128x32_fn
,
U8G_COM_SSD_I2C
);
uint8_t
u8g_dev_ssd1306_128x32_2x_buf
[
WIDTH
*
2
]
U8G_NOCOMMON
;
u8g_pb_t
u8g_dev_ssd1306_128x32_2x_pb
=
{
{
16
,
HEIGHT
,
0
,
0
,
0
},
WIDTH
,
u8g_dev_ssd1306_128x32_2x_buf
};
u8g_dev_t
u8g_dev_ssd1306_128x32_2x_sw_spi
=
{
u8g_dev_ssd1306_128x32_2x_fn
,
&
u8g_dev_ssd1306_128x32_2x_pb
,
U8G_COM_SW_SPI
};
u8g_dev_t
u8g_dev_ssd1306_128x32_2x_hw_spi
=
{
u8g_dev_ssd1306_128x32_2x_fn
,
&
u8g_dev_ssd1306_128x32_2x_pb
,
U8G_COM_HW_SPI
};
u8g_dev_t
u8g_dev_ssd1306_128x32_2x_i2c
=
{
u8g_dev_ssd1306_128x32_2x_fn
,
&
u8g_dev_ssd1306_128x32_2x_pb
,
U8G_COM_SSD_I2C
};
app/u8glib/u8g_dev_ssd1306_128x64.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_ssd1306_128x64.c
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 64
#define PAGE_HEIGHT 8
/* init sequence adafruit 128x64 OLED (NOT TESTED) */
static
const
uint8_t
u8g_dev_ssd1306_128x64_adafruit1_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0ae
,
/* display off, sleep mode */
0x0d5
,
0x080
,
/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
0x0a8
,
0x03f
,
/* */
0x0d3
,
0x000
,
/* */
0x040
,
/* start line */
0x08d
,
0x010
,
/* [1] charge pump setting (p62): 0x014 enable, 0x010 disable */
0x020
,
0x000
,
/* */
0x0a1
,
/* segment remap a0/a1*/
0x0c8
,
/* c0: scan dir normal, c8: reverse */
0x0da
,
0x012
,
/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
0x081
,
0x09f
,
/* [1] set contrast control */
0x0d9
,
0x022
,
/* [1] pre-charge period 0x022/f1*/
0x0db
,
0x040
,
/* vcomh deselect level */
0x02e
,
/* 2012-05-27: Deactivate scroll */
0x0a4
,
/* output ram to display */
0x0a6
,
/* none inverted normal display mode */
0x0af
,
/* display on */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
/* init sequence adafruit 128x64 OLED (NOT TESTED) */
static
const
uint8_t
u8g_dev_ssd1306_128x64_adafruit2_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0ae
,
/* display off, sleep mode */
0x0d5
,
0x080
,
/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
0x0a8
,
0x03f
,
/* */
0x0d3
,
0x000
,
/* */
0x040
,
/* start line */
0x08d
,
0x014
,
/* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
0x020
,
0x000
,
/* */
0x0a1
,
/* segment remap a0/a1*/
0x0c8
,
/* c0: scan dir normal, c8: reverse */
0x0da
,
0x012
,
/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
0x081
,
0x0cf
,
/* [2] set contrast control */
0x0d9
,
0x0f1
,
/* [2] pre-charge period 0x022/f1*/
0x0db
,
0x040
,
/* vcomh deselect level */
0x02e
,
/* 2012-05-27: Deactivate scroll */
0x0a4
,
/* output ram to display */
0x0a6
,
/* none inverted normal display mode */
0x0af
,
/* display on */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
/* init sequence adafruit 128x64 OLED (NOT TESTED), like adafruit3, but with page addressing mode */
static
const
uint8_t
u8g_dev_ssd1306_128x64_adafruit3_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0ae
,
/* display off, sleep mode */
0x0d5
,
0x080
,
/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
0x0a8
,
0x03f
,
/* */
0x0d3
,
0x000
,
/* */
0x040
,
/* start line */
0x08d
,
0x014
,
/* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
0x020
,
0x002
,
/* 2012-05-27: page addressing mode */
0x0a1
,
/* segment remap a0/a1*/
0x0c8
,
/* c0: scan dir normal, c8: reverse */
0x0da
,
0x012
,
/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
0x081
,
0x0cf
,
/* [2] set contrast control */
0x0d9
,
0x0f1
,
/* [2] pre-charge period 0x022/f1*/
0x0db
,
0x040
,
/* vcomh deselect level */
0x02e
,
/* 2012-05-27: Deactivate scroll */
0x0a4
,
/* output ram to display */
0x0a6
,
/* none inverted normal display mode */
0x0af
,
/* display on */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
/* init sequence Univision datasheet (NOT TESTED) */
static
const
uint8_t
u8g_dev_ssd1306_128x64_univision_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0ae
,
/* display off, sleep mode */
0x0d5
,
0x080
,
/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
0x0a8
,
0x03f
,
/* multiplex ratio */
0x0d3
,
0x000
,
/* display offset */
0x040
,
/* start line */
0x08d
,
0x010
,
/* charge pump setting (p62): 0x014 enable, 0x010 disable */
0x0a1
,
/* segment remap a0/a1*/
0x0c8
,
/* c0: scan dir normal, c8: reverse */
0x0da
,
0x012
,
/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
0x081
,
0x09f
,
/* set contrast control */
0x0d9
,
0x022
,
/* pre-charge period */
0x0db
,
0x040
,
/* vcomh deselect level */
0x022
,
0x000
,
/* page addressing mode WRONG: 3 byte cmd! */
0x0a4
,
/* output ram to display */
0x0a6
,
/* none inverted normal display mode */
0x0af
,
/* display on */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
/* select one init sequence here */
//#define u8g_dev_ssd1306_128x64_init_seq u8g_dev_ssd1306_128x64_univision_init_seq
//#define u8g_dev_ssd1306_128x64_init_seq u8g_dev_ssd1306_128x64_adafruit1_init_seq
// 26. Apr 2014: in this thead: http://forum.arduino.cc/index.php?topic=234930.msg1696754;topicseen#msg1696754
// it is mentiond, that adafruit2_init_seq works better --> this will be used by the ssd1306_adafruit device
//#define u8g_dev_ssd1306_128x64_init_seq u8g_dev_ssd1306_128x64_adafruit2_init_seq
#define u8g_dev_ssd1306_128x64_init_seq u8g_dev_ssd1306_128x64_adafruit3_init_seq
static
const
uint8_t
u8g_dev_ssd1306_128x64_data_start
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x010
,
/* set upper 4 bit of the col adr to 0 */
0x000
,
/* set lower 4 bit of the col adr to 0 */
U8G_ESC_END
/* end of sequence */
};
/* the sh1106 is compatible to the ssd1306, but is 132x64. display seems to be centered */
static
const
uint8_t
u8g_dev_sh1106_128x64_data_start
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x010
,
/* set upper 4 bit of the col adr to 0 */
0x002
,
/* set lower 4 bit of the col adr to 2 (centered display with sh1106) */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ssd13xx_sleep_on
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0ae
,
/* display off */
U8G_ESC_CS
(
0
),
/* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ssd13xx_sleep_off
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0af
,
/* display on */
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_CS
(
0
),
/* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END
/* end of sequence */
};
uint8_t
u8g_dev_ssd1306_128x64_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_300NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_128x64_adafruit2_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_128x64_data_start
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b0
|
pb
->
p
.
page
);
/* select current page (SSD1306) */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
if
(
u8g_pb_WriteBuffer
(
pb
,
u8g
,
dev
)
==
0
)
return
0
;
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_off
);
return
1
;
case
U8G_DEV_MSG_CONTRAST
:
{
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x81
);
u8g_WriteByte
(
u8g
,
dev
,
*
(
uint8_t
*
)
arg
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
return
1
;
}
}
return
u8g_dev_pb8v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
uint8_t
u8g_dev_ssd1306_adafruit_128x64_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_300NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_128x64_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_128x64_data_start
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b0
|
pb
->
p
.
page
);
/* select current page (SSD1306) */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
if
(
u8g_pb_WriteBuffer
(
pb
,
u8g
,
dev
)
==
0
)
return
0
;
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_off
);
return
1
;
case
U8G_DEV_MSG_CONTRAST
:
{
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x81
);
u8g_WriteByte
(
u8g
,
dev
,
*
(
uint8_t
*
)
arg
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
return
1
;
}
}
return
u8g_dev_pb8v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
uint8_t
u8g_dev_sh1106_128x64_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_300NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_128x64_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_sh1106_128x64_data_start
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b0
|
pb
->
p
.
page
);
/* select current page (SSD1306) */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
if
(
u8g_pb_WriteBuffer
(
pb
,
u8g
,
dev
)
==
0
)
return
0
;
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_off
);
return
1
;
case
U8G_DEV_MSG_CONTRAST
:
{
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x81
);
u8g_WriteByte
(
u8g
,
dev
,
*
(
uint8_t
*
)
arg
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
return
1
;
}
}
return
u8g_dev_pb8v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
uint8_t
u8g_dev_ssd1306_128x64_2x_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_300NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_128x64_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_128x64_data_start
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b0
|
(
pb
->
p
.
page
*
2
));
/* select current page (SSD1306) */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
pb
->
width
,
pb
->
buf
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_128x64_data_start
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b0
|
(
pb
->
p
.
page
*
2
+
1
));
/* select current page (SSD1306) */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
pb
->
width
,
(
uint8_t
*
)(
pb
->
buf
)
+
pb
->
width
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_off
);
return
1
;
case
U8G_DEV_MSG_CONTRAST
:
{
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x81
);
u8g_WriteByte
(
u8g
,
dev
,
*
(
uint8_t
*
)
arg
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
return
1
;
}
}
return
u8g_dev_pb16v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
uint8_t
u8g_dev_sh1106_128x64_2x_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_300NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_128x64_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_sh1106_128x64_data_start
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b0
|
(
pb
->
p
.
page
*
2
));
/* select current page (SSD1306) */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
pb
->
width
,
pb
->
buf
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_sh1106_128x64_data_start
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b0
|
(
pb
->
p
.
page
*
2
+
1
));
/* select current page (SSD1306) */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
pb
->
width
,
(
uint8_t
*
)(
pb
->
buf
)
+
pb
->
width
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_off
);
return
1
;
case
U8G_DEV_MSG_CONTRAST
:
{
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x81
);
u8g_WriteByte
(
u8g
,
dev
,
*
(
uint8_t
*
)
arg
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
return
1
;
}
}
return
u8g_dev_pb16v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
U8G_PB_DEV
(
u8g_dev_ssd1306_128x64_sw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1306_128x64_fn
,
U8G_COM_SW_SPI
);
U8G_PB_DEV
(
u8g_dev_ssd1306_128x64_hw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1306_128x64_fn
,
U8G_COM_HW_SPI
);
U8G_PB_DEV
(
u8g_dev_ssd1306_128x64_i2c
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1306_128x64_fn
,
U8G_COM_SSD_I2C
);
U8G_PB_DEV
(
u8g_dev_ssd1306_adafruit_128x64_sw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1306_adafruit_128x64_fn
,
U8G_COM_SW_SPI
);
U8G_PB_DEV
(
u8g_dev_ssd1306_adafruit_128x64_hw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1306_adafruit_128x64_fn
,
U8G_COM_HW_SPI
);
U8G_PB_DEV
(
u8g_dev_ssd1306_adafruit_128x64_i2c
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1306_adafruit_128x64_fn
,
U8G_COM_SSD_I2C
);
uint8_t
u8g_dev_ssd1306_128x64_2x_buf
[
WIDTH
*
2
]
U8G_NOCOMMON
;
u8g_pb_t
u8g_dev_ssd1306_128x64_2x_pb
=
{
{
16
,
HEIGHT
,
0
,
0
,
0
},
WIDTH
,
u8g_dev_ssd1306_128x64_2x_buf
};
u8g_dev_t
u8g_dev_ssd1306_128x64_2x_sw_spi
=
{
u8g_dev_ssd1306_128x64_2x_fn
,
&
u8g_dev_ssd1306_128x64_2x_pb
,
U8G_COM_SW_SPI
};
u8g_dev_t
u8g_dev_ssd1306_128x64_2x_hw_spi
=
{
u8g_dev_ssd1306_128x64_2x_fn
,
&
u8g_dev_ssd1306_128x64_2x_pb
,
U8G_COM_HW_SPI
};
u8g_dev_t
u8g_dev_ssd1306_128x64_2x_i2c
=
{
u8g_dev_ssd1306_128x64_2x_fn
,
&
u8g_dev_ssd1306_128x64_2x_pb
,
U8G_COM_SSD_I2C
};
U8G_PB_DEV
(
u8g_dev_sh1106_128x64_sw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_sh1106_128x64_fn
,
U8G_COM_SW_SPI
);
U8G_PB_DEV
(
u8g_dev_sh1106_128x64_hw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_sh1106_128x64_fn
,
U8G_COM_HW_SPI
);
U8G_PB_DEV
(
u8g_dev_sh1106_128x64_i2c
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_sh1106_128x64_fn
,
U8G_COM_SSD_I2C
);
uint8_t
u8g_dev_sh1106_128x64_2x_buf
[
WIDTH
*
2
]
U8G_NOCOMMON
;
u8g_pb_t
u8g_dev_sh1106_128x64_2x_pb
=
{
{
16
,
HEIGHT
,
0
,
0
,
0
},
WIDTH
,
u8g_dev_sh1106_128x64_2x_buf
};
u8g_dev_t
u8g_dev_sh1106_128x64_2x_sw_spi
=
{
u8g_dev_sh1106_128x64_2x_fn
,
&
u8g_dev_sh1106_128x64_2x_pb
,
U8G_COM_SW_SPI
};
u8g_dev_t
u8g_dev_sh1106_128x64_2x_hw_spi
=
{
u8g_dev_sh1106_128x64_2x_fn
,
&
u8g_dev_sh1106_128x64_2x_pb
,
U8G_COM_HW_SPI
};
u8g_dev_t
u8g_dev_sh1106_128x64_2x_i2c
=
{
u8g_dev_sh1106_128x64_2x_fn
,
&
u8g_dev_sh1106_128x64_2x_pb
,
U8G_COM_SSD_I2C
};
app/u8glib/u8g_dev_ssd1306_64x48.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_ssd1306_64x48.c
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 64
#define HEIGHT 48
#define PAGE_HEIGHT 8
/* init sequence buydisplay.com 0.66" 64x48 OLED */
/* http://www.buydisplay.com/download/manual/ER-OLED0.66-1_Series_Datasheet.pdf */
static
const
uint8_t
u8g_dev_ssd1306_64x48_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0ae
,
/* display off, sleep mode */
0x0d5
,
0x080
,
/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
0x0a8
,
0x02f
,
/* Multiplex Ration, Jul 12, 2015: From 0.66" OLED datasheet */
0x0d3
,
0x000
,
/* */
0x040
,
/* start line */
0x08d
,
0x014
,
/* charge pump setting (p62): 0x014 enable, 0x010 disable */
//0x020, 0x002, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), Feb 23, 2013: 64x48 OLED: 0x002, 64x48 OLED 0x012 */
0x0a1
,
/* segment remap a0/a1*/
0x0c8
,
/* c0: scan dir normal, c8: reverse */
0x0da
,
0x012
,
/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), Jul 12, 2015: From 0.66" OLED datasheet */
0x081
,
0x0cf
,
/* set contrast control */
0x0d9
,
0x022
,
/* pre-charge period 0x022/f1, from 0.66" OLED datasheet */
0x0db
,
0x000
,
/* vcomh deselect level, from 0.66" OLED datasheet */
0x02e
,
/* 2012-05-27: Deactivate scroll */
0x0a4
,
/* output ram to display */
0x0a6
,
/* none inverted normal display mode */
0x0af
,
/* display on */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ssd1306_64x48_data_start
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x010
+
2
,
/* set upper 4 bit of the col adr. to 0, 0.66" OLED starts with offset 32 */
0x000
,
/* set lower 4 bit of the col adr. to 4 */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ssd13xx_sleep_on
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0ae
,
/* display off */
U8G_ESC_CS
(
0
),
/* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ssd13xx_sleep_off
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0af
,
/* display on */
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_CS
(
0
),
/* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END
/* end of sequence */
};
uint8_t
u8g_dev_ssd1306_64x48_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_300NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_64x48_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_64x48_data_start
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b0
|
pb
->
p
.
page
);
/* select current page (SSD1306) */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
if
(
u8g_pb_WriteBuffer
(
pb
,
u8g
,
dev
)
==
0
)
return
0
;
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
case
U8G_DEV_MSG_CONTRAST
:
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x081
);
u8g_WriteByte
(
u8g
,
dev
,
(
*
(
uint8_t
*
)
arg
)
);
/* 11 Jul 2015: fixed contrast calculation */
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
return
1
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_off
);
return
1
;
}
return
u8g_dev_pb8v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
uint8_t
u8g_dev_ssd1306_64x48_2x_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_300NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_64x48_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_64x48_data_start
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b0
|
(
pb
->
p
.
page
*
2
));
/* select current page (SSD1306) */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
pb
->
width
,
pb
->
buf
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1306_64x48_data_start
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b0
|
(
pb
->
p
.
page
*
2
+
1
));
/* select current page (SSD1306) */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteSequence
(
u8g
,
dev
,
pb
->
width
,
(
uint8_t
*
)(
pb
->
buf
)
+
pb
->
width
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
case
U8G_DEV_MSG_CONTRAST
:
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x081
);
u8g_WriteByte
(
u8g
,
dev
,
(
*
(
uint8_t
*
)
arg
)
);
/* 11 Jul 2015: fixed contrast calculation */
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
return
1
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_off
);
return
1
;
}
return
u8g_dev_pb16v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
U8G_PB_DEV
(
u8g_dev_ssd1306_64x48_sw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1306_64x48_fn
,
U8G_COM_SW_SPI
);
U8G_PB_DEV
(
u8g_dev_ssd1306_64x48_hw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1306_64x48_fn
,
U8G_COM_HW_SPI
);
U8G_PB_DEV
(
u8g_dev_ssd1306_64x48_i2c
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1306_64x48_fn
,
U8G_COM_SSD_I2C
);
uint8_t
u8g_dev_ssd1306_64x48_2x_buf
[
WIDTH
*
2
]
U8G_NOCOMMON
;
u8g_pb_t
u8g_dev_ssd1306_64x48_2x_pb
=
{
{
16
,
HEIGHT
,
0
,
0
,
0
},
WIDTH
,
u8g_dev_ssd1306_64x48_2x_buf
};
u8g_dev_t
u8g_dev_ssd1306_64x48_2x_sw_spi
=
{
u8g_dev_ssd1306_64x48_2x_fn
,
&
u8g_dev_ssd1306_64x48_2x_pb
,
U8G_COM_SW_SPI
};
u8g_dev_t
u8g_dev_ssd1306_64x48_2x_hw_spi
=
{
u8g_dev_ssd1306_64x48_2x_fn
,
&
u8g_dev_ssd1306_64x48_2x_pb
,
U8G_COM_HW_SPI
};
u8g_dev_t
u8g_dev_ssd1306_64x48_2x_i2c
=
{
u8g_dev_ssd1306_64x48_2x_fn
,
&
u8g_dev_ssd1306_64x48_2x_pb
,
U8G_COM_SSD_I2C
};
app/u8glib/u8g_dev_ssd1309_128x64.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_ssd1309_128x64.c
Universal 8bit Graphics Library
Copyright (c) 2012, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 64
#define PAGE_HEIGHT 8
/* ssd1309 ini sequence*/
static
const
uint8_t
u8g_dev_ssd1309_128x64_init_seq
[]
PROGMEM
=
{
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip */
0xfd
,
0x12
,
/*Command Lock */
0xae
,
/*Set Display Off */
0xd5
,
0xa0
,
/*set Display Clock Divide Ratio/Oscillator Frequency */
0xa8
,
0x3f
,
/*Set Multiplex Ratio */
0x3d
,
0x00
,
/*Set Display Offset*/
0x40
,
/*Set Display Start Line*/
0xa1
,
/*Set Segment Re-Map*/
0xc8
,
/*Set COM Output Scan Direction*/
0xda
,
0x12
,
/*Set COM Pins Hardware Configuration*/
0x81
,
0xdf
,
/*Set Current Control */
0xd9
,
0x82
,
/*Set Pre-Charge Period */
0xdb
,
0x34
,
/*Set VCOMH Deselect Level */
0xa4
,
/*Set Entire Display On/Off */
0xa6
,
/*Set Normal/Inverse Display*/
U8G_ESC_VCC
(
1
),
/*Power up VCC & Stabilized */
U8G_ESC_DLY
(
50
),
0xaf
,
/*Set Display On */
U8G_ESC_DLY
(
50
),
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
/* select one init sequence here */
#define u8g_dev_ssd1309_128x64_init_seq u8g_dev_ssd1309_128x64_init_seq
static
const
uint8_t
u8g_dev_ssd1309_128x64_data_start
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x010
,
/* set upper 4 bit of the col adr to 0 */
0x000
,
/* set lower 4 bit of the col adr to 4 */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ssd13xx_sleep_on
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0ae
,
/* display off */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ssd13xx_sleep_off
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0af
,
/* display on */
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
uint8_t
u8g_dev_ssd1309_128x64_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_300NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1309_128x64_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1309_128x64_data_start
);
u8g_WriteByte
(
u8g
,
dev
,
0x0b0
|
pb
->
p
.
page
);
/* select current page (SSD1306) */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
if
(
u8g_pb_WriteBuffer
(
pb
,
u8g
,
dev
)
==
0
)
return
0
;
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
}
break
;
case
U8G_DEV_MSG_CONTRAST
:
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x081
);
u8g_WriteByte
(
u8g
,
dev
,
(
*
(
uint8_t
*
)
arg
)
);
/* 11 Jul 2015: fixed contrast calculation */
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
return
1
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_off
);
return
1
;
}
return
u8g_dev_pb8v1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
U8G_PB_DEV
(
u8g_dev_ssd1309_128x64_hw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1309_128x64_fn
,
U8G_COM_HW_SPI
);
U8G_PB_DEV
(
u8g_dev_ssd1309_128x64_sw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1309_128x64_fn
,
U8G_COM_SW_SPI
);
U8G_PB_DEV
(
u8g_dev_ssd1309_128x64_i2c
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1309_128x64_fn
,
U8G_COM_SSD_I2C
);
app/u8glib/u8g_dev_ssd1322_nhd31oled_bw.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_ssd1322_nhd31oled_bw.c
1-Bit (BW) Driver for SSD1322 Controller (OLED Display)
Tested with NHD-3.12-25664
Universal 8bit Graphics Library
Copyright (c) 2012, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
SSD130x Monochrom OLED Controller
SSD131x Character OLED Controller
SSD132x Graylevel OLED Controller
SSD1331 Color OLED Controller
*/
#include "u8g.h"
/* width must be multiple of 8, largest value is 248 unless u8g 16 bit mode is enabled */
#if defined(U8G_16BIT)
#define WIDTH 256
#else
#define WIDTH 248
#endif
#define HEIGHT 64
#define PAGE_HEIGHT 8
/*
http://www.newhavendisplay.com/app_notes/OLED_25664.txt
http://www.newhavendisplay.com/forum/viewtopic.php?f=15&t=3758
*/
static
const
uint8_t
u8g_dev_ssd1322_1bit_nhd_312_init_seq
[]
PROGMEM
=
{
U8G_ESC_DLY
(
10
),
/* delay 10 ms */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip */
U8G_ESC_DLY
(
100
),
/* delay 100 ms */
U8G_ESC_DLY
(
100
),
/* delay 100 ms */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0fd
,
/* lock command */
U8G_ESC_ADR
(
1
),
/* data mode */
0x012
,
/* unlock */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0ae
,
/* display off, sleep mode */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0b3
,
U8G_ESC_ADR
(
1
),
/* data mode */
0x091
,
/* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec) */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0ca
,
/* multiplex ratio */
U8G_ESC_ADR
(
1
),
/* data mode */
0x03f
,
/* 1/64 Duty (0x0F~0x3F) */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0a2
,
U8G_ESC_ADR
(
1
),
/* data mode */
0x000
,
/* display offset, shift mapping ram counter */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0a1
,
U8G_ESC_ADR
(
1
),
/* data mode */
0x000
,
/* display start line */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0a0
,
/* Set Re-Map / Dual COM Line Mode */
U8G_ESC_ADR
(
1
),
/* data mode */
0x014
,
/* was 0x014 */
0x011
,
/* was 0x011 */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0ab
,
U8G_ESC_ADR
(
1
),
/* data mode */
0x001
,
/* Enable Internal VDD Regulator */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0b4
,
/* Display Enhancement A */
U8G_ESC_ADR
(
1
),
/* data mode */
0x0a0
,
0x005
|
0x0fd
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0c1
,
/* contrast */
U8G_ESC_ADR
(
1
),
/* data mode */
0x09f
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0c7
,
/* Set Scale Factor of Segment Output Current Control */
U8G_ESC_ADR
(
1
),
/* data mode */
0x00f
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0b9
,
/* linear gray scale */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0b1
,
/* Phase 1 (Reset) & Phase 2 (Pre-Charge) Period Adjustment */
U8G_ESC_ADR
(
1
),
/* data mode */
0x0e2
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0d1
,
/* Display Enhancement B */
U8G_ESC_ADR
(
1
),
/* data mode */
0x082
|
0x020
,
0x020
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0bb
,
/* precharge voltage */
U8G_ESC_ADR
(
1
),
/* data mode */
0x01f
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0b6
,
/* precharge period */
U8G_ESC_ADR
(
1
),
/* data mode */
0x008
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0be
,
/* vcomh */
U8G_ESC_ADR
(
1
),
/* data mode */
0x007
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0a6
,
/* normal display */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0a9
,
/* exit partial display */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0af
,
/* display on */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ssd1322_1bit_nhd_312_prepare_page_seq
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x015
,
/* column address... */
U8G_ESC_ADR
(
1
),
/* data mode */
0x01c
,
/* start at column 0 */
0x05b
,
/* end column */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x075
,
/* row address... */
U8G_ESC_ADR
(
1
),
/* data mode */
U8G_ESC_END
/* end of sequence */
};
static
void
u8g_dev_ssd1322_1bit_prepare_row
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
delta_row
)
{
uint8_t
row
=
((
u8g_pb_t
*
)(
dev
->
dev_mem
))
->
p
.
page
;
row
*=
((
u8g_pb_t
*
)(
dev
->
dev_mem
))
->
p
.
page_height
;
row
+=
delta_row
;
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1322_1bit_nhd_312_prepare_page_seq
);
u8g_WriteByte
(
u8g
,
dev
,
row
);
/* start at the selected row */
u8g_WriteByte
(
u8g
,
dev
,
row
+
1
);
/* end within the selected row */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode mode */
u8g_WriteByte
(
u8g
,
dev
,
0x05c
);
/* write to ram */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
}
static
const
uint8_t
u8g_dev_ssd13xx_sleep_on
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0ae
,
/* display off */
U8G_ESC_CS
(
0
),
/* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ssd13xx_sleep_off
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0af
,
/* display on */
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_CS
(
0
),
/* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END
/* end of sequence */
};
uint8_t
u8g_dev_ssd1322_nhd31oled_bw_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_300NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1322_1bit_nhd_312_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
uint8_t
i
;
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
uint8_t
*
p
=
pb
->
buf
;
u8g_uint_t
cnt
;
cnt
=
pb
->
width
;
cnt
>>=
3
;
for
(
i
=
0
;
i
<
pb
->
p
.
page_height
;
i
++
)
{
u8g_dev_ssd1322_1bit_prepare_row
(
u8g
,
dev
,
i
);
/* this will also enable chip select */
#if !defined(U8G_16BIT)
u8g_WriteByte
(
u8g
,
dev
,
0x0ff
);
u8g_WriteByte
(
u8g
,
dev
,
0x0ff
);
#endif
u8g_WriteSequenceBWTo16GrDevice
(
u8g
,
dev
,
cnt
,
p
);
#if !defined(U8G_16BIT)
u8g_WriteByte
(
u8g
,
dev
,
0x0ff
);
u8g_WriteByte
(
u8g
,
dev
,
0x0ff
);
#endif
u8g_MicroDelay
();
// for DUE?
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
p
+=
cnt
;
}
}
break
;
case
U8G_DEV_MSG_CONTRAST
:
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x081
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteByte
(
u8g
,
dev
,
(
*
(
uint8_t
*
)
arg
)
>>
1
);
u8g_MicroDelay
();
// for DUE?
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
break
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_off
);
return
1
;
}
return
u8g_dev_pb8h1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
uint8_t
u8g_dev_ssd1322_nhd31oled_2x_bw_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_300NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1322_1bit_nhd_312_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
uint8_t
i
;
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
uint8_t
*
p
=
pb
->
buf
;
u8g_uint_t
cnt
;
cnt
=
pb
->
width
;
cnt
>>=
3
;
for
(
i
=
0
;
i
<
pb
->
p
.
page_height
;
i
++
)
{
u8g_dev_ssd1322_1bit_prepare_row
(
u8g
,
dev
,
i
);
/* this will also enable chip select */
#if !defined(U8G_16BIT)
u8g_WriteByte
(
u8g
,
dev
,
0x0ff
);
u8g_WriteByte
(
u8g
,
dev
,
0x0ff
);
#endif
u8g_WriteSequenceBWTo16GrDevice
(
u8g
,
dev
,
cnt
,
p
);
#if !defined(U8G_16BIT)
u8g_WriteByte
(
u8g
,
dev
,
0x0ff
);
u8g_WriteByte
(
u8g
,
dev
,
0x0ff
);
#endif
u8g_MicroDelay
();
// for DUE?
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
p
+=
cnt
;
}
}
break
;
case
U8G_DEV_MSG_CONTRAST
:
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x0c1
);
/* 21 May 2013, fixed contrast command */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteByte
(
u8g
,
dev
,
(
*
(
uint8_t
*
)
arg
)
>>
1
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
break
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_off
);
return
1
;
}
return
u8g_dev_pb16h1_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
U8G_PB_DEV
(
u8g_dev_ssd1322_nhd31oled_bw_sw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1322_nhd31oled_bw_fn
,
U8G_COM_SW_SPI
);
U8G_PB_DEV
(
u8g_dev_ssd1322_nhd31oled_bw_hw_spi
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1322_nhd31oled_bw_fn
,
U8G_COM_HW_SPI
);
U8G_PB_DEV
(
u8g_dev_ssd1322_nhd31oled_bw_parallel
,
WIDTH
,
HEIGHT
,
PAGE_HEIGHT
,
u8g_dev_ssd1322_nhd31oled_bw_fn
,
U8G_COM_FAST_PARALLEL
);
#define DWIDTH (WIDTH*2)
uint8_t
u8g_dev_ssd1322_nhd31oled_2x_bw_buf
[
DWIDTH
]
U8G_NOCOMMON
;
u8g_pb_t
u8g_dev_ssd1322_nhd31oled_2x_bw_pb
=
{
{
16
,
HEIGHT
,
0
,
0
,
0
},
WIDTH
,
u8g_dev_ssd1322_nhd31oled_2x_bw_buf
};
u8g_dev_t
u8g_dev_ssd1322_nhd31oled_2x_bw_sw_spi
=
{
u8g_dev_ssd1322_nhd31oled_2x_bw_fn
,
&
u8g_dev_ssd1322_nhd31oled_2x_bw_pb
,
U8G_COM_SW_SPI
};
u8g_dev_t
u8g_dev_ssd1322_nhd31oled_2x_bw_hw_spi
=
{
u8g_dev_ssd1322_nhd31oled_2x_bw_fn
,
&
u8g_dev_ssd1322_nhd31oled_2x_bw_pb
,
U8G_COM_HW_SPI
};
app/u8glib/u8g_dev_ssd1322_nhd31oled_gr.c
deleted
100644 → 0
View file @
fd745e09
/*
u8g_dev_ssd1322_nhd31oled_gr.c
2-Bit (4L) Driver for SSD1322 Controller (OLED Display)
Tested with NHD-3.12-25664
Universal 8bit Graphics Library
Copyright (c) 2012, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
SSD130x Monochrom OLED Controller
SSD131x Character OLED Controller
SSD132x Graylevel OLED Controller
SSD1331 Color OLED Controller
*/
#include "u8g.h"
/* width must be multiple of 8, largest value is 248 unless u8g 16 bit mode is enabled */
#if defined(U8G_16BIT)
#define WIDTH 256
#else
#define WIDTH 248
#endif
#define HEIGHT 64
//#define PAGE_HEIGHT 8
/*
http://www.newhavendisplay.com/app_notes/OLED_25664.txt
http://www.newhavendisplay.com/forum/viewtopic.php?f=15&t=3758
*/
static
const
uint8_t
u8g_dev_ssd1322_2bit_nhd_312_init_seq
[]
PROGMEM
=
{
U8G_ESC_DLY
(
10
),
/* delay 10 ms */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_RST
(
1
),
/* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS
(
1
),
/* enable chip */
U8G_ESC_DLY
(
100
),
/* delay 100 ms */
U8G_ESC_DLY
(
100
),
/* delay 100 ms */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0fd
,
/* lock command */
U8G_ESC_ADR
(
1
),
/* data mode */
0x012
,
/* unlock */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0ae
,
/* display off, sleep mode */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0b3
,
U8G_ESC_ADR
(
1
),
/* data mode */
0x091
,
/* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec) */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0ca
,
/* multiplex ratio */
U8G_ESC_ADR
(
1
),
/* data mode */
0x03f
,
/* 1/64 Duty (0x0F~0x3F) */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0a2
,
U8G_ESC_ADR
(
1
),
/* data mode */
0x000
,
/* display offset, shift mapping ram counter */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0a1
,
U8G_ESC_ADR
(
1
),
/* data mode */
0x000
,
/* display start line */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0a0
,
/* Set Re-Map / Dual COM Line Mode */
U8G_ESC_ADR
(
1
),
/* data mode */
0x014
,
/* was 0x014 */
0x011
,
/* was 0x011 */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0ab
,
U8G_ESC_ADR
(
1
),
/* data mode */
0x001
,
/* Enable Internal VDD Regulator */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0b4
,
/* Display Enhancement A */
U8G_ESC_ADR
(
1
),
/* data mode */
0x0a0
,
0x005
|
0x0fd
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0c1
,
/* contrast */
U8G_ESC_ADR
(
1
),
/* data mode */
0x09f
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0c7
,
/* Set Scale Factor of Segment Output Current Control */
U8G_ESC_ADR
(
1
),
/* data mode */
0x00f
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0b9
,
/* linear gray scale */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0b1
,
/* Phase 1 (Reset) & Phase 2 (Pre-Charge) Period Adjustment */
U8G_ESC_ADR
(
1
),
/* data mode */
0x0e2
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0d1
,
/* Display Enhancement B */
U8G_ESC_ADR
(
1
),
/* data mode */
0x082
|
0x020
,
0x020
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0bb
,
/* precharge voltage */
U8G_ESC_ADR
(
1
),
/* data mode */
0x01f
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0b6
,
/* precharge period */
U8G_ESC_ADR
(
1
),
/* data mode */
0x008
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0be
,
/* vcomh */
U8G_ESC_ADR
(
1
),
/* data mode */
0x007
,
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0a6
,
/* normal display */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0a9
,
/* exit partial display */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x0af
,
/* display on */
U8G_ESC_CS
(
0
),
/* disable chip */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ssd1322_2bit_nhd_312_prepare_page_seq
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x015
,
/* column address... */
U8G_ESC_ADR
(
1
),
/* data mode */
0x01c
,
/* start at column 0 */
0x05b
,
/* end column */
U8G_ESC_ADR
(
0
),
/* instruction mode */
0x075
,
/* row address... */
U8G_ESC_ADR
(
1
),
/* data mode */
U8G_ESC_END
/* end of sequence */
};
static
void
u8g_dev_ssd1322_2bit_prepare_row
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
delta_row
)
{
uint8_t
row
=
((
u8g_pb_t
*
)(
dev
->
dev_mem
))
->
p
.
page
;
row
*=
((
u8g_pb_t
*
)(
dev
->
dev_mem
))
->
p
.
page_height
;
row
+=
delta_row
;
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1322_2bit_nhd_312_prepare_page_seq
);
u8g_WriteByte
(
u8g
,
dev
,
row
);
/* start at the selected row */
u8g_WriteByte
(
u8g
,
dev
,
row
+
1
);
/* end within the selected row */
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode mode */
u8g_WriteByte
(
u8g
,
dev
,
0x05c
);
/* write to ram */
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
}
static
const
uint8_t
u8g_dev_ssd13xx_sleep_on
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0ae
,
/* display off */
U8G_ESC_CS
(
0
),
/* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END
/* end of sequence */
};
static
const
uint8_t
u8g_dev_ssd13xx_sleep_off
[]
PROGMEM
=
{
U8G_ESC_ADR
(
0
),
/* instruction mode */
U8G_ESC_CS
(
1
),
/* enable chip */
0x0af
,
/* display on */
U8G_ESC_DLY
(
50
),
/* delay 50 ms */
U8G_ESC_CS
(
0
),
/* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END
/* end of sequence */
};
uint8_t
u8g_dev_ssd1322_nhd31oled_gr_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_300NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1322_2bit_nhd_312_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
uint8_t
i
;
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
uint8_t
*
p
=
pb
->
buf
;
u8g_uint_t
cnt
;
cnt
=
pb
->
width
;
cnt
>>=
2
;
for
(
i
=
0
;
i
<
pb
->
p
.
page_height
;
i
++
)
{
u8g_dev_ssd1322_2bit_prepare_row
(
u8g
,
dev
,
i
);
/* this will also enable chip select */
#if !defined(U8G_16BIT)
u8g_WriteByte
(
u8g
,
dev
,
0x00
);
u8g_WriteByte
(
u8g
,
dev
,
0x00
);
#endif
u8g_WriteSequence4LTo16GrDevice
(
u8g
,
dev
,
cnt
,
p
);
#if !defined(U8G_16BIT)
u8g_WriteByte
(
u8g
,
dev
,
0x00
);
u8g_WriteByte
(
u8g
,
dev
,
0x00
);
#endif
u8g_MicroDelay
();
// for DUE?
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
p
+=
cnt
;
}
}
break
;
case
U8G_DEV_MSG_CONTRAST
:
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x081
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteByte
(
u8g
,
dev
,
(
*
(
uint8_t
*
)
arg
)
>>
1
);
u8g_MicroDelay
();
// for DUE?
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
break
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_off
);
return
1
;
}
return
u8g_dev_pb8h2_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
uint8_t
u8g_dev_ssd1322_nhd31oled_2x_gr_fn
(
u8g_t
*
u8g
,
u8g_dev_t
*
dev
,
uint8_t
msg
,
void
*
arg
)
{
switch
(
msg
)
{
case
U8G_DEV_MSG_INIT
:
u8g_InitCom
(
u8g
,
dev
,
U8G_SPI_CLK_CYCLE_300NS
);
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd1322_2bit_nhd_312_init_seq
);
break
;
case
U8G_DEV_MSG_STOP
:
break
;
case
U8G_DEV_MSG_PAGE_NEXT
:
{
uint8_t
i
;
u8g_pb_t
*
pb
=
(
u8g_pb_t
*
)(
dev
->
dev_mem
);
uint8_t
*
p
=
pb
->
buf
;
u8g_uint_t
cnt
;
cnt
=
pb
->
width
;
cnt
>>=
2
;
/* 23 Oct 2013, changed to 2 */
for
(
i
=
0
;
i
<
pb
->
p
.
page_height
;
i
++
)
{
u8g_dev_ssd1322_2bit_prepare_row
(
u8g
,
dev
,
i
);
/* this will also enable chip select */
#if !defined(U8G_16BIT)
u8g_WriteByte
(
u8g
,
dev
,
0x00
);
u8g_WriteByte
(
u8g
,
dev
,
0x00
);
#endif
u8g_WriteSequence4LTo16GrDevice
(
u8g
,
dev
,
cnt
,
p
);
#if !defined(U8G_16BIT)
u8g_WriteByte
(
u8g
,
dev
,
0x00
);
u8g_WriteByte
(
u8g
,
dev
,
0x00
);
#endif
u8g_MicroDelay
();
// for DUE?
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
p
+=
cnt
;
}
}
break
;
case
U8G_DEV_MSG_CONTRAST
:
u8g_SetChipSelect
(
u8g
,
dev
,
1
);
u8g_SetAddress
(
u8g
,
dev
,
0
);
/* instruction mode */
u8g_WriteByte
(
u8g
,
dev
,
0x081
);
u8g_SetAddress
(
u8g
,
dev
,
1
);
/* data mode */
u8g_WriteByte
(
u8g
,
dev
,
(
*
(
uint8_t
*
)
arg
)
>>
1
);
u8g_SetChipSelect
(
u8g
,
dev
,
0
);
break
;
case
U8G_DEV_MSG_SLEEP_ON
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_on
);
return
1
;
case
U8G_DEV_MSG_SLEEP_OFF
:
u8g_WriteEscSeqP
(
u8g
,
dev
,
u8g_dev_ssd13xx_sleep_off
);
return
1
;
}
return
u8g_dev_pb16h2_base_fn
(
u8g
,
dev
,
msg
,
arg
);
}
U8G_PB_DEV
(
u8g_dev_ssd1322_nhd31oled_gr_sw_spi
,
WIDTH
,
HEIGHT
,
4
,
u8g_dev_ssd1322_nhd31oled_gr_fn
,
U8G_COM_SW_SPI
);
U8G_PB_DEV
(
u8g_dev_ssd1322_nhd31oled_gr_hw_spi
,
WIDTH
,
HEIGHT
,
4
,
u8g_dev_ssd1322_nhd31oled_gr_fn
,
U8G_COM_HW_SPI
);
U8G_PB_DEV
(
u8g_dev_ssd1322_nhd31oled_gr_parallel
,
WIDTH
,
HEIGHT
,
4
,
u8g_dev_ssd1322_nhd31oled_gr_fn
,
U8G_COM_FAST_PARALLEL
);
#define DWIDTH (WIDTH*2)
uint8_t
u8g_dev_ssd1322_nhd31oled_2x_gr_buf
[
DWIDTH
]
U8G_NOCOMMON
;
u8g_pb_t
u8g_dev_ssd1322_nhd31oled_2x_gr_pb
=
{
{
8
,
HEIGHT
,
0
,
0
,
0
},
WIDTH
,
u8g_dev_ssd1322_nhd31oled_2x_gr_buf
};
u8g_dev_t
u8g_dev_ssd1322_nhd31oled_2x_gr_sw_spi
=
{
u8g_dev_ssd1322_nhd31oled_2x_gr_fn
,
&
u8g_dev_ssd1322_nhd31oled_2x_gr_pb
,
U8G_COM_SW_SPI
};
u8g_dev_t
u8g_dev_ssd1322_nhd31oled_2x_gr_hw_spi
=
{
u8g_dev_ssd1322_nhd31oled_2x_gr_fn
,
&
u8g_dev_ssd1322_nhd31oled_2x_gr_pb
,
U8G_COM_HW_SPI
};
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