Commit 224788b6 authored by Johny Mattsson's avatar Johny Mattsson
Browse files

Make NodeMCU compile and link for ESP32.

A fair bit of reshuffling with include paths and overrides was necessary, as
the two RTOS SDKs (ESP8266 and ESP32) don't have the same header structure
(or even libraries for that matter). Uses the xtensa-esp108-elf toolchain
to build.

Completely untested beyond linking, as I still can't flash the ESP32 module
I have :(  I'd be most surprised if it does anything useful at this point
considering I've spent almost no time on the linker script or UART setup.

Anything using espconn has been ifdef'd out since espconn is not (and
probably will not be) available. Notably this includes the entire net module
as well as coap, mqtt and enduser_setup.

Many (most?) hardware bus drivers and related modules are also ifdef'd
out for now due to hardware differences. Functions surrounding sleep,
rtc and RF modes have also been hit by the ifdef hammer. Grep'ing for
__ESP8266__ and/or FIXME is a quick way of finding these places. With
time I hope all of these will be reinstated.
parent 0df2eda6
......@@ -3,7 +3,7 @@
#include "platform.h"
#include <stdlib.h>
#include <string.h>
#include "esp_misc.h"
#include "user_interface.h"
#include "rom.h"
/**
......
#ifndef _CPU_ESP32_H_
#define _CPU_ESP32_H_
#include <stdint.h>
#include <stdbool.h>
#include "user_config.h"
#include <spi_flash.h>
#include <eagle_soc.h>
#include <gpio.h>
#include <gpio/io_mux_reg.h>
#include <gpio/gpio_reg.h>
#include "flash_api.h"
#include "pin_map.h"
/* FIXME: real numbers here! */
#define NUM_GPIO GPIO_PIN_NUM
#define NUM_SPI 2
#define NUM_UART 1
#define NUM_PWM GPIO_PIN_NUM
#define NUM_ADC 1
#define NUM_CAN 0
#define NUM_I2C 1
#define NUM_OW GPIO_PIN_NUM
#define NUM_TMR 7
#if defined(FLASH_512K)
# define FLASH_SEC_NUM 0x80 // 4MByte: 0x400, 2MByte: 0x200, 1MByte: 0x100, 512KByte: 0x80
#elif defined(FLASH_1M)
# define FLASH_SEC_NUM 0x100
#elif defined(FLASH_2M)
# define FLASH_SEC_NUM 0x200
#elif defined(FLASH_4M)
# define FLASH_SEC_NUM 0x400
#elif defined(FLASH_8M)
# define FLASH_SEC_NUM 0x800
#elif defined(FLASH_16M)
# define FLASH_SEC_NUM 0x1000
#elif defined(FLASH_AUTOSIZE)
# if defined(FLASH_SAFE_API)
# define FLASH_SEC_NUM (flash_safe_get_sec_num())
# else
# define FLASH_SEC_NUM (flash_rom_get_sec_num())
# endif // defined(FLASH_SAFE_API)
#else
# define FLASH_SEC_NUM 0x80
#endif
#define SYS_PARAM_SEC_NUM 4
#define SYS_PARAM_SEC_START (FLASH_SEC_NUM - SYS_PARAM_SEC_NUM)
#define INTERNAL_FLASH_SECTOR_SIZE SPI_FLASH_SEC_SIZE
// #define INTERNAL_FLASH_SECTOR_ARRAY { 0x4000, 0x4000, 0x4000, 0x4000, 0x10000, 0x20000, 0x20000, 0x20000, 0x20000, 0x20000 }
#define INTERNAL_FLASH_WRITE_UNIT_SIZE 4
#define INTERNAL_FLASH_READ_UNIT_SIZE 4
#define INTERNAL_FLASH_SIZE ( (SYS_PARAM_SEC_START) * INTERNAL_FLASH_SECTOR_SIZE )
// TODO: double-check flash mapped address
#define INTERNAL_FLASH_MAPPED_ADDRESS 0x40084000
#if defined(FLASH_SAFE_API)
#define flash_write flash_safe_write
#define flash_erase flash_safe_erase_sector
#define flash_read flash_safe_read
#else
#define flash_write spi_flash_write
#define flash_erase spi_flash_erase_sector
#define flash_read spi_flash_read
#endif // defined(FLASH_SAFE_API)
#endif
......@@ -23,26 +23,27 @@
#define NUM_TMR 7
#if defined(FLASH_512K)
#define FLASH_SEC_NUM 0x80 // 4MByte: 0x400, 2MByte: 0x200, 1MByte: 0x100, 512KByte: 0x80
# define FLASH_SEC_NUM 0x80 // 4MByte: 0x400, 2MByte: 0x200, 1MByte: 0x100, 512KByte: 0x80
#elif defined(FLASH_1M)
#define FLASH_SEC_NUM 0x100
# define FLASH_SEC_NUM 0x100
#elif defined(FLASH_2M)
#define FLASH_SEC_NUM 0x200
# define FLASH_SEC_NUM 0x200
#elif defined(FLASH_4M)
#define FLASH_SEC_NUM 0x400
# define FLASH_SEC_NUM 0x400
#elif defined(FLASH_8M)
#define FLASH_SEC_NUM 0x800
# define FLASH_SEC_NUM 0x800
#elif defined(FLASH_16M)
#define FLASH_SEC_NUM 0x1000
# define FLASH_SEC_NUM 0x1000
#elif defined(FLASH_AUTOSIZE)
#if defined(FLASH_SAFE_API)
#define FLASH_SEC_NUM (flash_safe_get_sec_num())
#else
#define FLASH_SEC_NUM (flash_rom_get_sec_num())
#endif // defined(FLASH_SAFE_API)
# if defined(FLASH_SAFE_API)
# define FLASH_SEC_NUM (flash_safe_get_sec_num())
# else
# define FLASH_SEC_NUM (flash_rom_get_sec_num())
# endif // defined(FLASH_SAFE_API)
#else
#define FLASH_SEC_NUM 0x80
# define FLASH_SEC_NUM 0x80
#endif
#define SYS_PARAM_SEC_NUM 4
#define SYS_PARAM_SEC_START (FLASH_SEC_NUM - SYS_PARAM_SEC_NUM)
......@@ -54,9 +55,6 @@
#define INTERNAL_FLASH_SIZE ( (SYS_PARAM_SEC_START) * INTERNAL_FLASH_SECTOR_SIZE )
#define INTERNAL_FLASH_MAPPED_ADDRESS 0x40200000
// SpiFlashOpResult spi_flash_erase_sector(uint16 sec);
// SpiFlashOpResult spi_flash_write(uint32 des_addr, uint32 *src_addr, uint32 size);
// SpiFlashOpResult spi_flash_read(uint32 src_addr, uint32 *des_addr, uint32 size);
#if defined(FLASH_SAFE_API)
#define flash_write flash_safe_write
#define flash_erase flash_safe_erase_sector
......
......@@ -7,6 +7,8 @@
#include "flash_api.h"
#include "spi_flash.h"
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
uint32_t flash_detect_size_byte(void)
{
......
......@@ -2,7 +2,7 @@
#define __FLASH_API_H__
#include "ets_sys.h"
#include "user_config.h"
#include "cpu_esp8266.h"
#include "platform.h"
#define FLASH_SIZE_2MBIT (2 * 1024 * 1024)
#define FLASH_SIZE_4MBIT (4 * 1024 * 1024)
......@@ -20,15 +20,21 @@
#define FLASH_SIZE_8MBYTE (FLASH_SIZE_64MBIT / 8)
#define FLASH_SIZE_16MBYTE (FLASH_SIZE_128MBIT/ 8)
#define FLASH_SAFEMODE_ENTER() \
#if defined(__ESP8266__)
# define FLASH_SAFEMODE_ENTER() \
do { \
extern SpiFlashChip flashchip; \
flashchip.chip_size = FLASH_SIZE_16MBYTE
#define FLASH_SAFEMODE_LEAVE() \
# define FLASH_SAFEMODE_LEAVE() \
flashchip.chip_size = flash_rom_get_size_byte(); \
} while(0)
#elif defined(__ESP32__)
// TODO: is there something similar to SpiFlashChip available on the ESP32?
# define FLASH_SAFEMODE_ENTER() do{}while(0)
# define FLASH_SAFEMODE_LEAVE() do{}while(0)
#endif
/******************************************************************************
* ROM Function definition
......
......@@ -12,7 +12,7 @@
*
* The owner parameter should be a unique value per module using this API
* It could be a pointer to a bit of data or code
* e.g. #define OWNER ((os_param_t) module_init)
* e.g. #define OWNER ((uint32_t) module_init)
* where module_init is a function. For builtin modules, it might be
* a small numeric value that is known not to clash.
*******************************************************************************/
......@@ -37,20 +37,20 @@ typedef enum { //timer interrupt mode
TM_EDGE_INT = 0, //edge interrupt
} TIMER_INT_MODE;
static os_param_t the_owner;
static os_param_t callback_arg;
static void (* user_hw_timer_cb)(os_param_t);
static uint32_t the_owner;
static uint32_t callback_arg;
static void (* user_hw_timer_cb)(uint32_t);
#define VERIFY_OWNER(owner) if (owner != the_owner) { if (the_owner) { return 0; } the_owner = owner; }
/******************************************************************************
* FunctionName : platform_hw_timer_arm_ticks
* Description : set a trigger timer delay for this timer.
* Parameters : os_param_t owner
* Parameters : uint32_t owner
* uint32 ticks :
* Returns : true if it worked
*******************************************************************************/
bool ICACHE_RAM_ATTR platform_hw_timer_arm_ticks(os_param_t owner, uint32_t ticks)
bool ICACHE_RAM_ATTR platform_hw_timer_arm_ticks(uint32_t owner, uint32_t ticks)
{
VERIFY_OWNER(owner);
RTC_REG_WRITE(FRC1_LOAD_ADDRESS, ticks);
......@@ -61,7 +61,7 @@ bool ICACHE_RAM_ATTR platform_hw_timer_arm_ticks(os_param_t owner, uint32_t tick
/******************************************************************************
* FunctionName : platform_hw_timer_arm_us
* Description : set a trigger timer delay for this timer.
* Parameters : os_param_t owner
* Parameters : uint32_t owner
* uint32 microseconds :
* in autoload mode
* 50 ~ 0x7fffff; for FRC1 source.
......@@ -70,7 +70,7 @@ bool ICACHE_RAM_ATTR platform_hw_timer_arm_ticks(os_param_t owner, uint32_t tick
* 10 ~ 0x7fffff;
* Returns : true if it worked
*******************************************************************************/
bool ICACHE_RAM_ATTR platform_hw_timer_arm_us(os_param_t owner, uint32_t microseconds)
bool ICACHE_RAM_ATTR platform_hw_timer_arm_us(uint32_t owner, uint32_t microseconds)
{
VERIFY_OWNER(owner);
RTC_REG_WRITE(FRC1_LOAD_ADDRESS, US_TO_RTC_TIMER_TICKS(microseconds));
......@@ -81,13 +81,13 @@ bool ICACHE_RAM_ATTR platform_hw_timer_arm_us(os_param_t owner, uint32_t microse
/******************************************************************************
* FunctionName : platform_hw_timer_set_func
* Description : set the func, when trigger timer is up.
* Parameters : os_param_t owner
* void (* user_hw_timer_cb_set)(os_param_t):
* Parameters : uint32_t owner
* void (* user_hw_timer_cb_set)(uint32_t):
timer callback function
* os_param_t arg
* uint32_t arg
* Returns : true if it worked
*******************************************************************************/
bool platform_hw_timer_set_func(os_param_t owner, void (* user_hw_timer_cb_set)(os_param_t), os_param_t arg)
bool platform_hw_timer_set_func(uint32_t owner, void (* user_hw_timer_cb_set)(uint32_t), uint32_t arg)
{
VERIFY_OWNER(owner);
callback_arg = arg;
......@@ -112,10 +112,10 @@ static void ICACHE_RAM_ATTR hw_timer_nmi_cb(void)
/******************************************************************************
* FunctionName : platform_hw_timer_get_delay_ticks
* Description : figure out how long since th last timer interrupt
* Parameters : os_param_t owner
* Parameters : uint32_t owner
* Returns : the number of ticks
*******************************************************************************/
uint32_t ICACHE_RAM_ATTR platform_hw_timer_get_delay_ticks(os_param_t owner)
uint32_t ICACHE_RAM_ATTR platform_hw_timer_get_delay_ticks(uint32_t owner)
{
VERIFY_OWNER(owner);
......@@ -125,7 +125,7 @@ uint32_t ICACHE_RAM_ATTR platform_hw_timer_get_delay_ticks(os_param_t owner)
/******************************************************************************
* FunctionName : platform_hw_timer_init
* Description : initialize the hardware isr timer
* Parameters : os_param_t owner
* Parameters : uint32_t owner
* FRC1_TIMER_SOURCE_TYPE source_type:
* FRC1_SOURCE, timer use frc1 isr as isr source.
* NMI_SOURCE, timer use nmi isr as isr source.
......@@ -134,7 +134,7 @@ uint32_t ICACHE_RAM_ATTR platform_hw_timer_get_delay_ticks(os_param_t owner)
* 1, autoload mode,
* Returns : true if it worked
*******************************************************************************/
bool platform_hw_timer_init(os_param_t owner, FRC1_TIMER_SOURCE_TYPE source_type, bool autoload)
bool platform_hw_timer_init(uint32_t owner, FRC1_TIMER_SOURCE_TYPE source_type, bool autoload)
{
VERIFY_OWNER(owner);
if (autoload) {
......@@ -162,10 +162,10 @@ bool platform_hw_timer_init(os_param_t owner, FRC1_TIMER_SOURCE_TYPE source_type
/******************************************************************************
* FunctionName : platform_hw_timer_close
* Description : ends use of the hardware isr timer
* Parameters : os_param_t owner
* Parameters : uint32_t owner
* Returns : true if it worked
*******************************************************************************/
bool ICACHE_RAM_ATTR platform_hw_timer_close(os_param_t owner)
bool ICACHE_RAM_ATTR platform_hw_timer_close(uint32_t owner)
{
VERIFY_OWNER(owner);
......
......@@ -20,17 +20,17 @@ typedef enum {
NMI_SOURCE = 1,
} FRC1_TIMER_SOURCE_TYPE;
bool ICACHE_RAM_ATTR platform_hw_timer_arm_ticks(os_param_t owner, uint32_t ticks);
bool ICACHE_RAM_ATTR platform_hw_timer_arm_ticks(uint32_t owner, uint32_t ticks);
bool ICACHE_RAM_ATTR platform_hw_timer_arm_us(os_param_t owner, uint32_t microseconds);
bool ICACHE_RAM_ATTR platform_hw_timer_arm_us(uint32_t owner, uint32_t microseconds);
bool platform_hw_timer_set_func(os_param_t owner, void (* user_hw_timer_cb_set)(os_param_t), os_param_t arg);
bool platform_hw_timer_set_func(uint32_t owner, void (* user_hw_timer_cb_set)(uint32_t), uint32_t arg);
bool platform_hw_timer_init(os_param_t owner, FRC1_TIMER_SOURCE_TYPE source_type, bool autoload);
bool platform_hw_timer_init(uint32_t owner, FRC1_TIMER_SOURCE_TYPE source_type, bool autoload);
bool ICACHE_RAM_ATTR platform_hw_timer_close(os_param_t owner);
bool ICACHE_RAM_ATTR platform_hw_timer_close(uint32_t owner);
uint32_t ICACHE_RAM_ATTR platform_hw_timer_get_delay_ticks(os_param_t owner);
uint32_t ICACHE_RAM_ATTR platform_hw_timer_get_delay_ticks(uint32_t owner);
#endif
......@@ -17,6 +17,7 @@ typedef struct {
uint8 intr_type;
} pin_rec;
#define DECLARE_PIN(n,p) { (PERIPHS_IO_MUX_##p##_U - PERIPHS_IO_MUX), n, FUNC_GPIO##n, GPIO_PIN_INTR_DISABLE}
#if defined(__ESP8266__)
static const pin_rec pin_map[] = {
{PAD_XPD_DCDC_CONF - PERIPHS_IO_MUX, 16, 0, GPIO_PIN_INTR_DISABLE},
DECLARE_PIN( 5, GPIO5),
......@@ -32,6 +33,11 @@ static const pin_rec pin_map[] = {
DECLARE_PIN( 9, SD_DATA2),
DECLARE_PIN(10, SD_DATA3)
};
#elif defined(__ESP32__)
// FIXME: fill in
static const pin_rec pin_map[] = {};
#endif
void get_pin_map(void) {
/*
* Flash copy of the pin map. This has to be copied to RAM to be accessible from the ISR.
......
......@@ -6,8 +6,14 @@
#include "user_config.h"
#include "gpio.h"
#define GPIO_PIN_NUM 13
#define GPIO_PIN_NUM_INV 17
#if defined(__ESP8266__)
# define GPIO_PIN_NUM 13
# define GPIO_PIN_NUM_INV 17
#elif defined (__ESP32__)
// FIXME: real numbers here...
# define GPIO_PIN_NUM 33
# define GPIO_PIN_NUM_INV 17
#endif
extern uint32_t pin_mux[GPIO_PIN_NUM];
extern uint8_t pin_num[GPIO_PIN_NUM];
......
......@@ -42,6 +42,7 @@ int platform_init()
return PLATFORM_OK;
}
#ifdef __ESP2866__
// ****************************************************************************
// KEY_LED functions
uint8_t platform_key_led( uint8_t level){
......@@ -53,6 +54,7 @@ uint8_t platform_key_led( uint8_t level){
gpio16_output_set(level);
return temp;
}
#endif
// ****************************************************************************
// GPIO functions
......@@ -107,6 +109,7 @@ int platform_gpio_mode( unsigned pin, unsigned mode, unsigned pull )
if (pin >= NUM_GPIO)
return -1;
#ifdef __ESP8266__
if(pin == 0){
if(mode==PLATFORM_GPIO_INPUT)
gpio16_input_conf();
......@@ -115,6 +118,7 @@ int platform_gpio_mode( unsigned pin, unsigned mode, unsigned pull )
return 1;
}
#endif
#ifdef LUA_USE_MODULES_PWM
platform_pwm_close(pin); // closed from pwm module, if it is used in pwm
......@@ -156,11 +160,14 @@ int platform_gpio_write( unsigned pin, unsigned level )
// NODE_DBG("Function platform_gpio_write() is called. pin:%d, level:%d\n",GPIO_ID_PIN(pin_num[pin]),level);
if (pin >= NUM_GPIO)
return -1;
#ifdef __ESP8266__
if(pin == 0){
gpio16_output_conf();
gpio16_output_set(level);
return 1;
}
#endif
GPIO_OUTPUT_SET(GPIO_ID_PIN(pin_num[pin]), level);
}
......@@ -171,10 +178,12 @@ int platform_gpio_read( unsigned pin )
if (pin >= NUM_GPIO)
return -1;
#ifdef __ESP8266__
if(pin == 0){
// gpio16_input_conf();
return 0x1 & gpio16_input_get();
}
#endif
// GPIO_DIS_OUTPUT(pin_num[pin]);
return 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(pin_num[pin]));
......@@ -448,15 +457,20 @@ uint32_t platform_pwm_get_clock( unsigned pin )
// NODE_DBG("Function platform_pwm_get_clock() is called.\n");
if( pin >= NUM_PWM)
return 0;
#ifdef __ESP8266__ // FIXME
if(!pwm_exist(pin))
return 0;
return (uint32_t)pwm_get_freq(pin);
#else
return 0;
#endif
}
// Set the PWM clock
uint32_t platform_pwm_set_clock( unsigned pin, uint32_t clock )
{
#ifdef __ESP8266__ // FIXME
// NODE_DBG("Function platform_pwm_set_clock() is called.\n");
if( pin >= NUM_PWM)
return 0;
......@@ -466,10 +480,14 @@ uint32_t platform_pwm_set_clock( unsigned pin, uint32_t clock )
pwm_set_freq((uint16_t)clock, pin);
pwm_start();
return (uint32_t)pwm_get_freq( pin );
#else
return 0;
#endif
}
uint32_t platform_pwm_get_duty( unsigned pin )
{
#ifdef __ESP8266__ // FIXME
// NODE_DBG("Function platform_pwm_get_duty() is called.\n");
if( pin < NUM_PWM){
if(!pwm_exist(pin))
......@@ -477,12 +495,14 @@ uint32_t platform_pwm_get_duty( unsigned pin )
// return NORMAL_DUTY(pwm_get_duty(pin));
return pwms_duty[pin];
}
#endif
return 0;
}
// Set the PWM duty
uint32_t platform_pwm_set_duty( unsigned pin, uint32_t duty )
{
#ifdef __ESP8266__ // FIXME
// NODE_DBG("Function platform_pwm_set_duty() is called.\n");
if ( pin < NUM_PWM)
{
......@@ -494,12 +514,14 @@ uint32_t platform_pwm_set_duty( unsigned pin, uint32_t duty )
}
pwm_start();
pwms_duty[pin] = NORMAL_DUTY(pwm_get_duty(pin));
#endif
return pwms_duty[pin];
}
uint32_t platform_pwm_setup( unsigned pin, uint32_t frequency, unsigned duty )
{
uint32_t clock;
#ifdef __ESP8266__ // FIXME
if ( pin < NUM_PWM)
{
platform_gpio_mode(pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT); // disable gpio interrupt first
......@@ -516,6 +538,7 @@ uint32_t platform_pwm_setup( unsigned pin, uint32_t frequency, unsigned duty )
if (!pwm_start()) {
return 0;
}
#endif
return clock;
}
......@@ -524,13 +547,16 @@ void platform_pwm_close( unsigned pin )
// NODE_DBG("Function platform_pwm_stop() is called.\n");
if ( pin < NUM_PWM)
{
#ifdef __ESP8266__ // FIXME
pwm_delete(pin);
#endif
pwm_start();
}
}
bool platform_pwm_start( unsigned pin )
{
#ifdef __ESP8266__ // FIXME
// NODE_DBG("Function platform_pwm_start() is called.\n");
if ( pin < NUM_PWM)
{
......@@ -539,12 +565,13 @@ bool platform_pwm_start( unsigned pin )
pwm_set_duty(DUTY(pwms_duty[pin]), pin);
return pwm_start();
}
#endif
return FALSE;
}
void platform_pwm_stop( unsigned pin )
{
#ifdef __ESP8266__ // FIXME
// NODE_DBG("Function platform_pwm_stop() is called.\n");
if ( pin < NUM_PWM)
{
......@@ -553,6 +580,7 @@ void platform_pwm_stop( unsigned pin )
pwm_set_duty(0, pin);
pwm_start();
}
#endif
}
......@@ -561,6 +589,7 @@ void platform_pwm_stop( unsigned pin )
uint8_t platform_sigma_delta_setup( uint8_t pin )
{
#ifdef __ESP8266__ // FIXME
if (pin < 1 || pin > NUM_GPIO)
return 0;
......@@ -575,11 +604,13 @@ uint8_t platform_sigma_delta_setup( uint8_t pin )
(GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
GPIO_PIN_SOURCE_SET( SIGMA_AS_PIN_SOURCE ));
#endif
return 1;
}
uint8_t platform_sigma_delta_close( uint8_t pin )
{
#ifdef __ESP8266__ // FIXME
if (pin < 1 || pin > NUM_GPIO)
return 0;
......@@ -593,11 +624,13 @@ uint8_t platform_sigma_delta_close( uint8_t pin )
(GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
GPIO_PIN_SOURCE_SET( GPIO_AS_PIN_SOURCE ));
#endif
return 1;
}
void platform_sigma_delta_set_pwmduty( uint8_t duty )
{
#ifdef __ESP8266__ // FIXME
uint8_t target = 0, prescale = 0;
target = duty > 128 ? 256 - duty : duty;
......@@ -605,16 +638,21 @@ void platform_sigma_delta_set_pwmduty( uint8_t duty )
//freq = 80000 (khz) /256 /duty_target * (prescale+1)
sigma_delta_set_prescale_target( prescale, duty );
#endif
}
void platform_sigma_delta_set_prescale( uint8_t prescale )
{
#ifdef __ESP8266__ // FIXME
sigma_delta_set_prescale_target( prescale, -1 );
#endif
}
void platform_sigma_delta_set_target( uint8_t target )
{
#ifdef __ESP8266__ // FIXME
sigma_delta_set_prescale_target( -1, target );
#endif
}
......@@ -673,7 +711,9 @@ int platform_i2c_recv_byte( unsigned id, int ack ){
// SPI platform interface
uint32_t platform_spi_setup( uint8_t id, int mode, unsigned cpol, unsigned cpha, uint32_t clock_div)
{
#ifdef __ESP8266__ // FIXME
spi_master_init( id, cpol, cpha, clock_div );
#endif
return 1;
}
......@@ -682,7 +722,9 @@ int platform_spi_send( uint8_t id, uint8_t bitlen, spi_data_type data )
if (bitlen > 32)
return PLATFORM_ERR;
#ifdef __ESP8266__ // FIXME
spi_mast_transaction( id, 0, 0, bitlen, data, 0, 0, 0 );
#endif
return PLATFORM_OK;
}
......@@ -691,9 +733,13 @@ spi_data_type platform_spi_send_recv( uint8_t id, uint8_t bitlen, spi_data_type
if (bitlen > 32)
return 0;
#ifdef __ESP8266__ // FIXME
spi_mast_set_mosi( id, 0, bitlen, data );
spi_mast_transaction( id, 0, 0, 0, 0, bitlen, 0, -1 );
return spi_mast_get_miso( id, 0, bitlen );
#else
return 0;
#endif
}
int platform_spi_set_mosi( uint8_t id, uint16_t offset, uint8_t bitlen, spi_data_type data )
......@@ -701,8 +747,9 @@ int platform_spi_set_mosi( uint8_t id, uint16_t offset, uint8_t bitlen, spi_data
if (offset + bitlen > 512)
return PLATFORM_ERR;
#ifdef __ESP8266__ // FIXME
spi_mast_set_mosi( id, offset, bitlen, data );
#endif
return PLATFORM_OK;
}
......@@ -711,7 +758,11 @@ spi_data_type platform_spi_get_miso( uint8_t id, uint16_t offset, uint8_t bitlen
if (offset + bitlen > 512)
return 0;
#ifdef __ESP8266__ // FIXME
return spi_mast_get_miso( id, offset, bitlen );
#else
return 0;
#endif
}
int platform_spi_transaction( uint8_t id, uint8_t cmd_bitlen, spi_data_type cmd_data,
......@@ -725,7 +776,9 @@ int platform_spi_transaction( uint8_t id, uint8_t cmd_bitlen, spi_data_type cmd_
(miso_bitlen > 512))
return PLATFORM_ERR;
#ifdef __ESP8266__ // FIXME
spi_mast_transaction( id, cmd_bitlen, cmd_data, addr_bitlen, addr_data, mosi_bitlen, dummy_bitlen, miso_bitlen );
#endif
return PLATFORM_OK;
}
......@@ -808,6 +861,7 @@ int platform_flash_erase_sector( uint32_t sector_id )
uint32_t platform_flash_mapped2phys (uint32_t mapped_addr)
{
#ifdef __ESP8266__
uint32_t cache_ctrl = READ_PERI_REG(CACHE_FLASH_CTRL_REG);
if (!(cache_ctrl & CACHE_FLASH_ACTIVE))
return -1;
......@@ -815,4 +869,8 @@ uint32_t platform_flash_mapped2phys (uint32_t mapped_addr)
bool b1 = (cache_ctrl & CACHE_FLASH_MAPPED1) ? 1 : 0;
uint32_t meg = (b1 << 1) | b0;
return mapped_addr - INTERNAL_FLASH_MAPPED_ADDRESS + meg * 0x100000;
#else
// FIXME
return mapped_addr - INTERNAL_FLASH_MAPPED_ADDRESS;
#endif
}
......@@ -3,7 +3,11 @@
#ifndef __PLATFORM_H__
#define __PLATFORM_H__
#include "cpu_esp8266.h"
#if defined(__ESP8266__)
# include "cpu_esp8266.h"
#elif defined(__ESP32__)
# include "cpu_esp32.h"
#endif
#include "c_types.h"
#include "driver/pwm.h"
......
......@@ -2,8 +2,10 @@
#include <stdlib.h>
#include <string.h>
#include "user_interface.h"
#include "user_config.h"
#include "smart.h"
#include "esp_wifi.h"
#include "esp_libc.h"
#define ADDR_MAP_NUM 10
......
......@@ -4,6 +4,8 @@
#include "task/task.h"
#include "mem.h"
#include "user_config.h"
#include <stdlib.h>
#include <string.h>
#include "freertos/queue.h"
#include "freertos/semphr.h"
......
......@@ -31,6 +31,7 @@
* @author Johny Mattsson <jmattsson@dius.com.au>
*/
#ifdef __ESP8266__
/* Exception handler for supporting non-32bit wide loads from mapped SPI flash
* (well, technically any mapped memory that can do 32bit loads). Pure assembly
......@@ -57,7 +58,6 @@
* the load functionality.
*/
/* frame save area, a0->a15, but a1=>sar */
.section ".data"
.align 4
......@@ -199,3 +199,5 @@ _UserExceptionVectorOverride:
1:call0 cause3_handler /* handle loads with rfe, stores will return here */
2:rsr a0, EXCSAVE1 /* restore a0 before we chain */
j _UserExceptionVector /* and off we go to rtos */
#endif
......@@ -32,6 +32,14 @@
#define SIG_LUA 0
#define SIG_UARTINPUT 1
#ifdef __ESP32__
void system_soft_wdt_feed (void)
{
// FIXME this shouldn't go here, and it needs to tickle hardware watchdog
}
#endif
extern void call_user_start (void);
......
......@@ -38,6 +38,7 @@
* have a minimal replacement printf() which omits the explicit flash-support
* support, and just calls the internal SDK function print() directly.
*/
#ifdef __ESP8266__
.section ".iram0.text"
.type __wrap_printf,@function
.globl __wrap_printf
......@@ -67,6 +68,7 @@ __wrap_printf:
l32i a0, a1, 0 /* restore return address into a0 */
addi a1, a1, 48 /* release the stack */
ret /* all done */
#endif
/* Flag for controlling whether SDK printf()s are suppressed or not.
* This is to provide an RTOS-safe reimplementation of system_set_os_print(). */
......
Subproject commit 8a83c7b706eecf80236a441b15bc2f80799ced78
/* boot.bin @ 0x00000 */
/* drom0.bin @ 0xX4000 */
/* irom0_flash.bin @ 0xX0000+0x40000 */
/* Flash Map */
/* |..|...............|...........................................|..| */
/* ^ ^ ^ ^ */
/* |_boot.bin(0x0000) |_irom0_flash.bin(0xX0000+0x40000) | */
/* |_drom0.bin(0xX4000) |_system param area(Flash size - 0x4000) */
/* RAM Map */
/* Pro CPU iRAM, Total len 0x28000 */
/* |......................................................| */
/* ^ */
/* |_iram1_0 : 0x40040000 (0x20000) */
/* |........| */
/* ^ */
/* |_cache for Pro CPU : (0x8000) */
/* Share Memory, Total len 0x28000 */
/* |..........| */
/* ^ */
/* |_dram0_0 : 0x3FFD8000 (dynamic len) */
/* |................................................| */
/* ^ */
/* |_ heap area */
/* |.....| */
/* ^ */
/* |_ used for Pro CPU's rom code : 0x3FFFC000 (0x4000) */
/* NOTICE: */
/* 1. drom0.bin + irom0_flash.bin = user.ota */
/* 2. drom0.bin and irom0_flash.bin must locate at 0xX4000 and 0xX0000+0x40000, */
/* here 0xX0000 must 256KB align. */
/* 3. Make sure each user.ota not overlap other. */
/* 4. Make sure each user.ota not overlap system param area or user param area. */
/* 5. We support a maximum of 5 user.ota */
/* 6. We support 1MB/2MB/4MB/8MB/16MB flash, */
/* but make suer user.ota not exceed 16MB. */
/* 7. rodata at drom0_0, drom0.bin. */
/* 8. Pay attention to any modification. */
MEMORY
{
dport0_0_seg : org = 0x3FF00000, len = 0x10
dram0_0_seg : org = 0x3FFD8000, len = 0x24000
iram1_0_seg : org = 0x40040000, len = 0x20000
irom0_0_seg : org = 0x40080010, len = 0x37FFF0
drom0_0_seg : org = 0x3FE04010, len = 0x3BFF0
}
PHDRS
{
dport0_0_phdr PT_LOAD;
dram0_0_phdr PT_LOAD;
iram1_0_phdr PT_LOAD;
irom0_0_phdr PT_LOAD;
drom0_0_phdr PT_LOAD;
}
/* Default entry point: */
ENTRY(call_user_start)
EXTERN(_Level2Vector)
EXTERN(_Level3Vector)
EXTERN(_Level4Vector)
EXTERN(_Level5Vector)
EXTERN(_DebugExceptionVector)
EXTERN(_NMIExceptionVector)
EXTERN(_KernelExceptionVector)
EXTERN(_DoubleExceptionVector)
PROVIDE(_memmap_vecbase_reset = 0x40000000);
/* Various memory-map dependent cache attribute settings: */
_memmap_cacheattr_wb_base = 0x00000110;
_memmap_cacheattr_wt_base = 0x00000110;
_memmap_cacheattr_bp_base = 0x00000220;
_memmap_cacheattr_unused_mask = 0xFFFFF00F;
_memmap_cacheattr_wb_trapnull = 0x2222211F;
_memmap_cacheattr_wba_trapnull = 0x2222211F;
_memmap_cacheattr_wbna_trapnull = 0x2222211F;
_memmap_cacheattr_wt_trapnull = 0x2222211F;
_memmap_cacheattr_bp_trapnull = 0x2222222F;
_memmap_cacheattr_wb_strict = 0xFFFFF11F;
_memmap_cacheattr_wt_strict = 0xFFFFF11F;
_memmap_cacheattr_bp_strict = 0xFFFFF22F;
_memmap_cacheattr_wb_allvalid = 0x22222112;
_memmap_cacheattr_wt_allvalid = 0x22222112;
_memmap_cacheattr_bp_allvalid = 0x22222222;
PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
SECTIONS
{
.dport0.rodata : ALIGN(4)
{
_dport0_rodata_start = ABSOLUTE(.);
*(.dport0.rodata)
*(.dport.rodata)
_dport0_rodata_end = ABSOLUTE(.);
} >dport0_0_seg :dport0_0_phdr
.dport0.literal : ALIGN(4)
{
_dport0_literal_start = ABSOLUTE(.);
*(.dport0.literal)
*(.dport.literal)
_dport0_literal_end = ABSOLUTE(.);
} >dport0_0_seg :dport0_0_phdr
.dport0.data : ALIGN(4)
{
_dport0_data_start = ABSOLUTE(.);
*(.dport0.data)
*(.dport.data)
_dport0_data_end = ABSOLUTE(.);
} >dport0_0_seg :dport0_0_phdr
.drom0.text : ALIGN(4)
{
_drom0_text_start = ABSOLUTE(.);
*(.drom0.literal .drom0.text.literal .drom0.text)
*(.rodata*)
_drom0_text_end = ABSOLUTE(.);
} >drom0_0_seg :drom0_0_phdr
.data : ALIGN(4)
{
_data_start = ABSOLUTE(.);
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.data1)
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
*(.jcr)
_data_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.rodata : ALIGN(4)
{
_rodata_start = ABSOLUTE(.);
*(.gnu.linkonce.r.*)
__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
*(.xt_except_table)
*(.gcc_except_table)
*(.gnu.linkonce.e.*)
*(.gnu.version_r)
*(.eh_frame)
. = (. + 3) & ~ 3;
/* C++ constructor and destructor tables, properly ordered: */
__init_array_start = ABSOLUTE(.);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__init_array_end = ABSOLUTE(.);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
/* C++ exception handlers table: */
__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
*(.xt_except_desc)
*(.gnu.linkonce.h.*)
__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
*(.xt_except_desc_end)
*(.dynamic)
*(.gnu.version_d)
. = ALIGN(4); /* this table MUST be 4-byte aligned */
_bss_table_start = ABSOLUTE(.);
LONG(_bss_start)
LONG(_bss_end)
_bss_table_end = ABSOLUTE(.);
_rodata_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.UserExceptionVector.literal : AT(LOADADDR(.rodata) + (ADDR(.UserExceptionVector.literal) - ADDR(.rodata))) ALIGN(4)
{
_UserExceptionVector_literal_start = ABSOLUTE(.);
*(.UserExceptionVector.literal)
_UserExceptionVector_literal_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.bss ALIGN(8) (NOLOAD) : ALIGN(4)
{
. = ALIGN (8);
_bss_start = ABSOLUTE(.);
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
*(.scommon)
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
*(.dynbss)
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN (8);
_bss_end = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
.share.mem (NOLOAD) : ALIGN(4)
{
_share_mem_start = ABSOLUTE(.);
*(.share.mem)
_share_mem_end = ABSOLUTE(.);
_heap_sentry = ABSOLUTE(.);
} >dram0_0_seg :dram0_0_phdr
_end = 0x3fffc000;
.text : ALIGN(4)
{
_stext = .;
_text_start = ABSOLUTE(.);
. = 0x0;
*(.WindowVectors.text)
. = 0x180;
*(.Level2InterruptVector.text)
. = 0x1c0;
*(.Level3InterruptVector.text)
. = 0x200;
*(.Level4InterruptVector.text)
. = 0x240;
*(.Level5InterruptVector.text)
. = 0x280;
*(.DebugExceptionVector.text)
. = 0x2c0;
*(.NMIExceptionVector.text)
. = 0x300;
*(.KernelExceptionVector.text)
. = 0x340;
*(.UserExceptionVector.text)
. = 0x3c0;
*(.DoubleExceptionVector.text)
. = 0x400;
*(.UserEnter.literal);
*(.UserEnter.text);
. = ALIGN (16);
*(.entry.text)
*(.init.literal)
*(.init)
*(.iram1.*)
*libmain.a:(.literal .text .literal.* .text.*)
*libfreertos.a:(.literal .text .literal.* .text.*)
*libpp.a:(.literal .text .literal.* .text.*)
*(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.fini.literal)
*(.fini)
*(.gnu.version)
_text_end = ABSOLUTE(.);
_etext = .;
} >iram1_0_seg :iram1_0_phdr
.irom0.text : ALIGN(4)
{
_irom0_text_start = ABSOLUTE(.);
*(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)
*(.literal .text .literal.* .text.*)
/* Link-time arrays containing the defs for the included modules */
. = ALIGN(4);
lua_libs = ABSOLUTE(.);
/* Allow either empty define or defined-to-1 to include the module */
KEEP(*(.lua_libs))
LONG(0) LONG(0) /* Null-terminate the array */
lua_rotable = ABSOLUTE(.);
KEEP(*(.lua_rotable))
LONG(0) LONG(0) /* Null-terminate the array */
_irom0_text_end = ABSOLUTE(.);
_flash_used_end = ABSOLUTE(.);
} >irom0_0_seg :irom0_0_phdr
.lit4 : ALIGN(4)
{
_lit4_start = ABSOLUTE(.);
*(*.lit4)
*(.lit4.*)
*(.gnu.linkonce.lit4.*)
_lit4_end = ABSOLUTE(.);
} >iram1_0_seg :iram1_0_phdr
}
INCLUDE "pro.rom.addr.ld"
#ifndef _SDK_OVERRIDES_ESP_LIBC_H_
#define _SDK_OVERRIDES_ESP_LIBC_H_
void *zalloc(size_t n);
#endif
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