Commit 4911d2db authored by Arnim Läuger's avatar Arnim Läuger
Browse files

Merge pull request #1336 from nodemcu/dev

1.5.1 master drop
parents c8037568 2e109686
/******************************************************************************
* Copyright 2013-2014 Espressif Systems (Wuxi)
*
* FileName: hw_timer.c
*
* Description: hw_timer driver
*
* Modification history:
* 2014/5/1, v1.0 create this file.
*
* Adapted for NodeMCU 2016
*
* The owner parameter should be a unique value per module using this API
* It could be a pointer to a bit of data or code
* e.g. #define OWNER ((os_param_t) module_init)
* where module_init is a function. For builtin modules, it might be
* a small numeric value that is known not to clash.
*******************************************************************************/
#include "ets_sys.h"
#include "os_type.h"
#include "osapi.h"
#include "hw_timer.h"
#define FRC1_ENABLE_TIMER BIT7
#define FRC1_AUTO_LOAD BIT6
//TIMER PREDIVIDED MODE
typedef enum {
DIVIDED_BY_1 = 0, //timer clock
DIVIDED_BY_16 = 4, //divided by 16
DIVIDED_BY_256 = 8, //divided by 256
} TIMER_PREDIVIDED_MODE;
typedef enum { //timer interrupt mode
TM_LEVEL_INT = 1, // level interrupt
TM_EDGE_INT = 0, //edge interrupt
} TIMER_INT_MODE;
static os_param_t the_owner;
static os_param_t callback_arg;
static void (* user_hw_timer_cb)(os_param_t);
#define VERIFY_OWNER(owner) if (owner != the_owner) { if (the_owner) { return 0; } the_owner = owner; }
/******************************************************************************
* FunctionName : platform_hw_timer_arm_ticks
* Description : set a trigger timer delay for this timer.
* Parameters : os_param_t owner
* uint32 ticks :
* Returns : true if it worked
*******************************************************************************/
bool ICACHE_RAM_ATTR platform_hw_timer_arm_ticks(os_param_t owner, uint32_t ticks)
{
VERIFY_OWNER(owner);
RTC_REG_WRITE(FRC1_LOAD_ADDRESS, ticks);
return 1;
}
/******************************************************************************
* FunctionName : platform_hw_timer_arm_us
* Description : set a trigger timer delay for this timer.
* Parameters : os_param_t owner
* uint32 microseconds :
* in autoload mode
* 50 ~ 0x7fffff; for FRC1 source.
* 100 ~ 0x7fffff; for NMI source.
* in non autoload mode:
* 10 ~ 0x7fffff;
* Returns : true if it worked
*******************************************************************************/
bool ICACHE_RAM_ATTR platform_hw_timer_arm_us(os_param_t owner, uint32_t microseconds)
{
VERIFY_OWNER(owner);
RTC_REG_WRITE(FRC1_LOAD_ADDRESS, US_TO_RTC_TIMER_TICKS(microseconds));
return 1;
}
/******************************************************************************
* FunctionName : platform_hw_timer_set_func
* Description : set the func, when trigger timer is up.
* Parameters : os_param_t owner
* void (* user_hw_timer_cb_set)(os_param_t):
timer callback function
* os_param_t arg
* Returns : true if it worked
*******************************************************************************/
bool platform_hw_timer_set_func(os_param_t owner, void (* user_hw_timer_cb_set)(os_param_t), os_param_t arg)
{
VERIFY_OWNER(owner);
callback_arg = arg;
user_hw_timer_cb = user_hw_timer_cb_set;
return 1;
}
static void ICACHE_RAM_ATTR hw_timer_isr_cb(void *arg)
{
if (user_hw_timer_cb != NULL) {
(*(user_hw_timer_cb))(callback_arg);
}
}
static void ICACHE_RAM_ATTR hw_timer_nmi_cb(void)
{
if (user_hw_timer_cb != NULL) {
(*(user_hw_timer_cb))(callback_arg);
}
}
/******************************************************************************
* FunctionName : platform_hw_timer_get_delay_ticks
* Description : figure out how long since th last timer interrupt
* Parameters : os_param_t owner
* Returns : the number of ticks
*******************************************************************************/
uint32_t ICACHE_RAM_ATTR platform_hw_timer_get_delay_ticks(os_param_t owner)
{
VERIFY_OWNER(owner);
return (- RTC_REG_READ(FRC1_COUNT_ADDRESS)) & ((1 << 23) - 1);
}
/******************************************************************************
* FunctionName : platform_hw_timer_init
* Description : initialize the hardware isr timer
* Parameters : os_param_t owner
* FRC1_TIMER_SOURCE_TYPE source_type:
* FRC1_SOURCE, timer use frc1 isr as isr source.
* NMI_SOURCE, timer use nmi isr as isr source.
* bool autoload:
* 0, not autoload,
* 1, autoload mode,
* Returns : true if it worked
*******************************************************************************/
bool platform_hw_timer_init(os_param_t owner, FRC1_TIMER_SOURCE_TYPE source_type, bool autoload)
{
VERIFY_OWNER(owner);
if (autoload) {
RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
FRC1_AUTO_LOAD | DIVIDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
} else {
RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
DIVIDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
}
if (source_type == NMI_SOURCE) {
ETS_FRC_TIMER1_NMI_INTR_ATTACH(hw_timer_nmi_cb);
} else {
ETS_FRC_TIMER1_INTR_ATTACH(hw_timer_isr_cb, NULL);
}
TM1_EDGE_INT_ENABLE();
ETS_FRC1_INTR_ENABLE();
return 1;
}
/******************************************************************************
* FunctionName : platform_hw_timer_close
* Description : ends use of the hardware isr timer
* Parameters : os_param_t owner
* Returns : true if it worked
*******************************************************************************/
bool ICACHE_RAM_ATTR platform_hw_timer_close(os_param_t owner)
{
VERIFY_OWNER(owner);
/* Set no reload mode */
RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
DIVIDED_BY_16 | TM_EDGE_INT);
TM1_EDGE_INT_DISABLE();
ETS_FRC1_INTR_DISABLE();
user_hw_timer_cb = NULL;
the_owner = 0;
return 1;
}
#ifndef _HW_TIMER_H
#define _HW_TIMER_H
#if APB_CLK_FREQ == 80 * 1000000
// 80 MHz divided by 16 is 5 MHz count rate.
#define US_TO_RTC_TIMER_TICKS(t) ((t) * 5)
#else
#define US_TO_RTC_TIMER_TICKS(t) \
((t) ? \
(((t) > 0x35A) ? \
(((t)>>2) * ((APB_CLK_FREQ>>4)/250000) + ((t)&0x3) * ((APB_CLK_FREQ>>4)/1000000)) : \
(((t) *(APB_CLK_FREQ>>4)) / 1000000)) : \
0)
#endif
typedef enum {
FRC1_SOURCE = 0,
NMI_SOURCE = 1,
} FRC1_TIMER_SOURCE_TYPE;
bool ICACHE_RAM_ATTR platform_hw_timer_arm_ticks(os_param_t owner, uint32_t ticks);
bool ICACHE_RAM_ATTR platform_hw_timer_arm_us(os_param_t owner, uint32_t microseconds);
bool platform_hw_timer_set_func(os_param_t owner, void (* user_hw_timer_cb_set)(os_param_t), os_param_t arg);
bool platform_hw_timer_init(os_param_t owner, FRC1_TIMER_SOURCE_TYPE source_type, bool autoload);
bool ICACHE_RAM_ATTR platform_hw_timer_close(os_param_t owner);
uint32_t ICACHE_RAM_ATTR platform_hw_timer_get_delay_ticks(os_param_t owner);
#endif
#include "pin_map.h"
#include "eagle_soc.h"
#if 0
uint32_t pin_mux[GPIO_PIN_NUM] = {PERIPHS_IO_MUX_MTDI_U, PERIPHS_IO_MUX_MTCK_U, PERIPHS_IO_MUX_MTMS_U, PERIPHS_IO_MUX_MTDO_U,
PERIPHS_IO_MUX_U0RXD_U, PERIPHS_IO_MUX_U0TXD_U, PERIPHS_IO_MUX_SD_DATA2_U, PERIPHS_IO_MUX_SD_DATA3_U,
PERIPHS_IO_MUX_GPIO0_U, PERIPHS_IO_MUX_GPIO2_U, PERIPHS_IO_MUX_GPIO4_U, PERIPHS_IO_MUX_GPIO5_U};
uint8_t pin_num[GPIO_PIN_NUM] = {12, 13, 14, 15,
3, 1, 9, 10,
0, 2, 4, 5};
uint8_t pin_func[GPIO_PIN_NUM] = {FUNC_GPIO12, FUNC_GPIO13, FUNC_GPIO14, FUNC_GPIO15,
FUNC_GPIO3, FUNC_GPIO1, FUNC_GPIO9, FUNC_GPIO10,
FUNC_GPIO0, FUNC_GPIO2, FUNC_GPIO4, FUNC_GPIO5};
#include "mem.h"
#include "osapi.h"
uint32_t pin_mux[GPIO_PIN_NUM];
uint8_t pin_num[GPIO_PIN_NUM];
uint8_t pin_func[GPIO_PIN_NUM];
#ifdef GPIO_INTERRUPT_ENABLE
GPIO_INT_TYPE pin_int_type[GPIO_PIN_NUM] = {
GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE,
GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE,
GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE};
uint8_t pin_num_inv[GPIO_PIN_NUM_INV];
uint8_t pin_int_type[GPIO_PIN_NUM];
#endif
#else
uint32_t pin_mux[GPIO_PIN_NUM] = {PAD_XPD_DCDC_CONF, PERIPHS_IO_MUX_GPIO5_U, PERIPHS_IO_MUX_GPIO4_U, PERIPHS_IO_MUX_GPIO0_U,
PERIPHS_IO_MUX_GPIO2_U, PERIPHS_IO_MUX_MTMS_U, PERIPHS_IO_MUX_MTDI_U, PERIPHS_IO_MUX_MTCK_U,
PERIPHS_IO_MUX_MTDO_U, PERIPHS_IO_MUX_U0RXD_U, PERIPHS_IO_MUX_U0TXD_U, PERIPHS_IO_MUX_SD_DATA2_U,
PERIPHS_IO_MUX_SD_DATA3_U };
uint8_t pin_num[GPIO_PIN_NUM] = {16, 5, 4, 0,
2, 14, 12, 13,
15, 3, 1, 9,
10};
uint8_t pin_func[GPIO_PIN_NUM] = {0, FUNC_GPIO5, FUNC_GPIO4, FUNC_GPIO0,
FUNC_GPIO2, FUNC_GPIO14, FUNC_GPIO12, FUNC_GPIO13,
FUNC_GPIO15, FUNC_GPIO3, FUNC_GPIO1, FUNC_GPIO9,
FUNC_GPIO10};
typedef struct {
int8 mux;
uint8 num;
uint8 func;
uint8 intr_type;
} pin_rec;
#define DECLARE_PIN(n,p) { (PERIPHS_IO_MUX_##p##_U - PERIPHS_IO_MUX), n, FUNC_GPIO##n, GPIO_PIN_INTR_DISABLE}
static const pin_rec pin_map[] = {
{PAD_XPD_DCDC_CONF - PERIPHS_IO_MUX, 16, 0, GPIO_PIN_INTR_DISABLE},
DECLARE_PIN( 5, GPIO5),
DECLARE_PIN( 4, GPIO4),
DECLARE_PIN( 0, GPIO0),
DECLARE_PIN( 2, GPIO2),
DECLARE_PIN(14, MTMS),
DECLARE_PIN(12, MTDI),
DECLARE_PIN(13, MTCK),
DECLARE_PIN(15, MTDO),
DECLARE_PIN( 3, U0RXD),
DECLARE_PIN( 1, U0TXD),
DECLARE_PIN( 9, SD_DATA2),
DECLARE_PIN(10, SD_DATA3)
};
void get_pin_map(void) {
/*
* Flash copy of the pin map. This has to be copied to RAM to be accessible from the ISR.
* Note that the mux field is a signed offset from PERIPHS_IO_MUX to allow the whole struct
* to be stored in a single 32-bit record.
*/
int i;
/* Take temporary stack copy to avoid unaligned exceptions on Flash version */
pin_rec pin[GPIO_PIN_NUM];
os_memcpy(pin, pin_map, sizeof(pin_map) );
for (i=0; i<GPIO_PIN_NUM; i++) {
pin_mux[i] = pin[i].mux + PERIPHS_IO_MUX;
pin_func[i] = pin[i].func;
pin_num[i] = pin[i].num;
#ifdef GPIO_INTERRUPT_ENABLE
GPIO_INT_TYPE pin_int_type[GPIO_PIN_NUM] = {
GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE,
GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE,
GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE, GPIO_PIN_INTR_DISABLE,
GPIO_PIN_INTR_DISABLE};
#endif
pin_num_inv[pin_num[i]] = i;
pin_int_type[i] = pin[i].intr_type;
#endif
}
}
......@@ -7,11 +7,16 @@
#include "gpio.h"
#define GPIO_PIN_NUM 13
#define GPIO_PIN_NUM_INV 17
extern uint32_t pin_mux[GPIO_PIN_NUM];
extern uint8_t pin_num[GPIO_PIN_NUM];
extern uint8_t pin_func[GPIO_PIN_NUM];
extern uint32_t pin_mux[GPIO_PIN_NUM];
#ifdef GPIO_INTERRUPT_ENABLE
extern GPIO_INT_TYPE pin_int_type[GPIO_PIN_NUM];
extern uint8_t pin_num_inv[GPIO_PIN_NUM_INV];
extern uint8_t pin_int_type[GPIO_PIN_NUM];
#endif
void get_pin_map(void);
#endif // #ifndef __PIN_MAP_H__
// Platform-dependent functions
// Platform-dependent functions and includes
#include "platform.h"
#include "common.h"
#include "c_stdio.h"
#include "c_string.h"
#include "c_stdlib.h"
#include "llimits.h"
#include "gpio.h"
#include "user_interface.h"
#include "driver/gpio16.h"
#include "driver/i2c_master.h"
#include "driver/spi.h"
#include "driver/uart.h"
// Platform specific includes
#include "driver/sigma_delta.h"
static void pwms_init();
#ifdef GPIO_INTERRUPT_ENABLE
static task_handle_t gpio_task_handle;
#ifdef GPIO_INTERRUPT_HOOK_ENABLE
struct gpio_hook_entry {
platform_hook_function func;
uint32_t bits;
};
struct gpio_hook {
struct gpio_hook_entry *entry;
uint32_t all_bits;
uint32_t count;
};
static struct gpio_hook platform_gpio_hook;
#endif
#endif
int platform_init()
{
// Setup PWMs
pwms_init();
// Setup the various forward and reverse mappings for the pins
get_pin_map();
cmn_platform_init();
// All done
......@@ -35,72 +56,101 @@ uint8_t platform_key_led( uint8_t level){
// ****************************************************************************
// GPIO functions
/*
* Set GPIO mode to output. Optionally in RAM helper because interrupts are dsabled
*/
static void NO_INTR_CODE set_gpio_no_interrupt(uint8 pin, uint8_t push_pull) {
unsigned pnum = pin_num[pin];
ETS_GPIO_INTR_DISABLE();
#ifdef GPIO_INTERRUPT_ENABLE
pin_int_type[pin] = GPIO_PIN_INTR_DISABLE;
#endif
PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
//disable interrupt
gpio_pin_intr_state_set(GPIO_ID_PIN(pnum), GPIO_PIN_INTR_DISABLE);
//clear interrupt status
GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pnum));
// configure push-pull vs open-drain
if (push_pull) {
GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) &
(~ GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE))); //disable open drain;
} else {
GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) |
GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); //enable open drain;
}
ETS_GPIO_INTR_ENABLE();
}
/*
* Set GPIO mode to interrupt. Optionally RAM helper because interrupts are dsabled
*/
#ifdef GPIO_INTERRUPT_ENABLE
extern void lua_gpio_unref(unsigned pin);
static void NO_INTR_CODE set_gpio_interrupt(uint8 pin) {
ETS_GPIO_INTR_DISABLE();
PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
GPIO_DIS_OUTPUT(pin_num[pin]);
gpio_register_set(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
GPIO_PIN_INT_TYPE_SET(GPIO_PIN_INTR_DISABLE)
| GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_DISABLE)
| GPIO_PIN_SOURCE_SET(GPIO_AS_PIN_SOURCE));
ETS_GPIO_INTR_ENABLE();
}
#endif
int platform_gpio_mode( unsigned pin, unsigned mode, unsigned pull )
{
// NODE_DBG("Function platform_gpio_mode() is called. pin_mux:%d, func:%d\n",pin_mux[pin],pin_func[pin]);
NODE_DBG("Function platform_gpio_mode() is called. pin_mux:%d, func:%d\n", pin_mux[pin], pin_func[pin]);
if (pin >= NUM_GPIO)
return -1;
if(pin == 0){
if(mode==PLATFORM_GPIO_INPUT)
gpio16_input_conf();
else
gpio16_output_conf();
return 1;
}
#ifdef LUA_USE_MODULES_PWM
platform_pwm_close(pin); // closed from pwm module, if it is used in pwm
#endif
switch(pull){
case PLATFORM_GPIO_PULLUP:
if (pull == PLATFORM_GPIO_PULLUP) {
PIN_PULLUP_EN(pin_mux[pin]);
break;
case PLATFORM_GPIO_FLOAT:
PIN_PULLUP_DIS(pin_mux[pin]);
break;
default:
} else {
PIN_PULLUP_DIS(pin_mux[pin]);
break;
}
switch(mode){
case PLATFORM_GPIO_INPUT:
#ifdef GPIO_INTERRUPT_ENABLE
lua_gpio_unref(pin); // unref the lua ref call back.
#endif
GPIO_DIS_OUTPUT(pin_num[pin]);
/* run on */
case PLATFORM_GPIO_OUTPUT:
ETS_GPIO_INTR_DISABLE();
#ifdef GPIO_INTERRUPT_ENABLE
pin_int_type[pin] = GPIO_PIN_INTR_DISABLE;
#endif
PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
//disable interrupt
gpio_pin_intr_state_set(GPIO_ID_PIN(pin_num[pin]), GPIO_PIN_INTR_DISABLE);
//clear interrupt status
GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pin_num[pin]));
GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])), GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) & (~ GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE))); //disable open drain;
ETS_GPIO_INTR_ENABLE();
set_gpio_no_interrupt(pin, TRUE);
break;
case PLATFORM_GPIO_OPENDRAIN:
set_gpio_no_interrupt(pin, FALSE);
break;
#ifdef GPIO_INTERRUPT_ENABLE
case PLATFORM_GPIO_INT:
ETS_GPIO_INTR_DISABLE();
PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
GPIO_DIS_OUTPUT(pin_num[pin]);
gpio_register_set(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])), GPIO_PIN_INT_TYPE_SET(GPIO_PIN_INTR_DISABLE)
| GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_DISABLE)
| GPIO_PIN_SOURCE_SET(GPIO_AS_PIN_SOURCE));
ETS_GPIO_INTR_ENABLE();
set_gpio_interrupt(pin);
break;
#endif
default:
break;
}
return 1;
}
int platform_gpio_write( unsigned pin, unsigned level )
{
// NODE_DBG("Function platform_gpio_write() is called. pin:%d, level:%d\n",GPIO_ID_PIN(pin_num[pin]),level);
......@@ -131,33 +181,137 @@ int platform_gpio_read( unsigned pin )
}
#ifdef GPIO_INTERRUPT_ENABLE
static void platform_gpio_intr_dispatcher( platform_gpio_intr_handler_fn_t cb){
uint8 i, level;
static void ICACHE_RAM_ATTR platform_gpio_intr_dispatcher (void *dummy){
uint32 j=0;
uint32 gpio_status = GPIO_REG_READ(GPIO_STATUS_ADDRESS);
for (i = 0; i < GPIO_PIN_NUM; i++) {
if (pin_int_type[i] && (gpio_status & BIT(pin_num[i])) ) {
UNUSED(dummy);
#ifdef GPIO_INTERRUPT_HOOK_ENABLE
if (gpio_status & platform_gpio_hook.all_bits) {
for (j = 0; j < platform_gpio_hook.count; j++) {
if (gpio_status & platform_gpio_hook.entry[j].bits)
gpio_status = (platform_gpio_hook.entry[j].func)(gpio_status);
}
}
#endif
/*
* gpio_status is a bit map where bit 0 is set if unmapped gpio pin 0 (pin3) has
* triggered the ISR. bit 1 if unmapped gpio pin 1 (pin10=U0TXD), etc. Since this
* is the ISR, it makes sense to optimize this by doing a fast scan of the status
* and reverse mapping any set bits.
*/
for (j = 0; gpio_status>0; j++, gpio_status >>= 1) {
if (gpio_status&1) {
int i = pin_num_inv[j];
if (pin_int_type[i]) {
//disable interrupt
gpio_pin_intr_state_set(GPIO_ID_PIN(pin_num[i]), GPIO_PIN_INTR_DISABLE);
gpio_pin_intr_state_set(GPIO_ID_PIN(j), GPIO_PIN_INTR_DISABLE);
//clear interrupt status
GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, gpio_status & BIT(pin_num[i]));
level = 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(pin_num[i]));
if(cb){
cb(i, level);
GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(j));
uint32 level = 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(j));
task_post_high (gpio_task_handle, (i<<1) + level);
// We re-enable the interrupt when we execute the callback
}
gpio_pin_intr_state_set(GPIO_ID_PIN(pin_num[i]), pin_int_type[i]);
}
}
}
void platform_gpio_init( platform_gpio_intr_handler_fn_t cb )
void platform_gpio_init( task_handle_t gpio_task )
{
ETS_GPIO_INTR_ATTACH(platform_gpio_intr_dispatcher, cb);
gpio_task_handle = gpio_task;
ETS_GPIO_INTR_ATTACH(platform_gpio_intr_dispatcher, NULL);
}
int platform_gpio_intr_init( unsigned pin, GPIO_INT_TYPE type )
#ifdef GPIO_INTERRUPT_HOOK_ENABLE
/*
* Register an ISR hook to be called from the GPIO ISR for a given GPIO bitmask.
* This routine is only called a few times so has been optimised for size and
* the unregister is a special case when the bits are 0.
*
* Each hook function can only be registered once. If it is re-registered
* then the hooked bits are just updated to the new value.
*/
int platform_gpio_register_intr_hook(uint32_t bits, platform_hook_function hook)
{
if (pin >= NUM_GPIO)
return -1;
struct gpio_hook nh, oh = platform_gpio_hook;
int i, j;
if (!hook) {
// Cannot register or unregister null hook
return 0;
}
int delete_slot = -1;
// If hook already registered, just update the bits
for (i=0; i<oh.count; i++) {
if (hook == oh.entry[i].func) {
if (!bits) {
// Unregister if move to zero bits
delete_slot = i;
break;
}
if (bits & (oh.all_bits & ~oh.entry[i].bits)) {
// Attempt to hook an already hooked bit
return 0;
}
// Update the hooked bits (in the right order)
uint32_t old_bits = oh.entry[i].bits;
*(volatile uint32_t *) &oh.entry[i].bits = bits;
*(volatile uint32_t *) &oh.all_bits = (oh.all_bits & ~old_bits) | bits;
return 1;
}
}
// This must be the register new hook / delete old hook
if (delete_slot < 0) {
if (bits & oh.all_bits) {
return 0; // Attempt to hook already hooked bits
}
nh.count = oh.count + 1; // register a new hook
} else {
nh.count = oh.count - 1; // unregister an old hook
}
// These return NULL if the count = 0 so only error check if > 0)
nh.entry = c_malloc( nh.count * sizeof(*(nh.entry)) );
if (nh.count && !(nh.entry)) {
return 0; // Allocation failure
}
for (i=0, j=0; i<oh.count; i++) {
// Don't copy if this is the entry to delete
if (i != delete_slot) {
nh.entry[j++] = oh.entry[i];
}
}
if (delete_slot < 0) { // for a register add the hook to the tail and set the all bits
nh.entry[j].bits = bits;
nh.entry[j].func = hook;
nh.all_bits = oh.all_bits | bits;
} else { // for an unregister clear the matching all bits
nh.all_bits = oh.all_bits & (~oh.entry[delete_slot].bits);
}
ETS_GPIO_INTR_DISABLE();
// This is a structure copy, so interrupts need to be disabled
platform_gpio_hook = nh;
ETS_GPIO_INTR_ENABLE();
c_free(oh.entry);
return 1;
}
#endif // GPIO_INTERRUPT_HOOK_ENABLE
/*
* Initialise GPIO interrupt mode. Optionally in RAM because interrupts are dsabled
*/
void NO_INTR_CODE platform_gpio_intr_init( unsigned pin, GPIO_INT_TYPE type )
{
if (platform_gpio_exists(pin)) {
ETS_GPIO_INTR_DISABLE();
//clear interrupt status
GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pin_num[pin]));
......@@ -165,6 +319,7 @@ int platform_gpio_intr_init( unsigned pin, GPIO_INT_TYPE type )
//enable interrupt
gpio_pin_intr_state_set(GPIO_ID_PIN(pin_num[pin]), type);
ETS_GPIO_INTR_ENABLE();
}
}
#endif
......@@ -190,6 +345,7 @@ uint32_t platform_uart_setup( unsigned id, uint32_t baud, int databits, int pari
case BIT_RATE_74880:
case BIT_RATE_115200:
case BIT_RATE_230400:
case BIT_RATE_256000:
case BIT_RATE_460800:
case BIT_RATE_921600:
case BIT_RATE_1843200:
......@@ -273,7 +429,7 @@ void platform_uart_send( unsigned id, u8 data )
static uint16_t pwms_duty[NUM_PWM] = {0};
static void pwms_init()
void platform_pwm_init()
{
int i;
for(i=0;i<NUM_PWM;i++){
......@@ -357,7 +513,9 @@ uint32_t platform_pwm_setup( unsigned pin, uint32_t frequency, unsigned duty )
return 0;
}
clock = platform_pwm_get_clock( pin );
pwm_start();
if (!pwm_start()) {
return 0;
}
return clock;
}
......@@ -371,16 +529,18 @@ void platform_pwm_close( unsigned pin )
}
}
void platform_pwm_start( unsigned pin )
bool platform_pwm_start( unsigned pin )
{
// NODE_DBG("Function platform_pwm_start() is called.\n");
if ( pin < NUM_PWM)
{
if(!pwm_exist(pin))
return;
return FALSE;
pwm_set_duty(DUTY(pwms_duty[pin]), pin);
pwm_start();
return pwm_start();
}
return FALSE;
}
void platform_pwm_stop( unsigned pin )
......@@ -395,6 +555,69 @@ void platform_pwm_stop( unsigned pin )
}
}
// *****************************************************************************
// Sigma-Delta platform interface
uint8_t platform_sigma_delta_setup( uint8_t pin )
{
if (pin < 1 || pin > NUM_GPIO)
return 0;
sigma_delta_setup();
// set GPIO output mode for this pin
platform_gpio_mode( pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT );
platform_gpio_write( pin, PLATFORM_GPIO_LOW );
// enable sigma-delta on this pin
GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
(GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
GPIO_PIN_SOURCE_SET( SIGMA_AS_PIN_SOURCE ));
return 1;
}
uint8_t platform_sigma_delta_close( uint8_t pin )
{
if (pin < 1 || pin > NUM_GPIO)
return 0;
sigma_delta_stop();
// set GPIO input mode for this pin
platform_gpio_mode( pin, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP );
// CONNECT GPIO TO PIN PAD
GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
(GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
GPIO_PIN_SOURCE_SET( GPIO_AS_PIN_SOURCE ));
return 1;
}
void platform_sigma_delta_set_pwmduty( uint8_t duty )
{
uint8_t target = 0, prescale = 0;
target = duty > 128 ? 256 - duty : duty;
prescale = target == 0 ? 0 : target-1;
//freq = 80000 (khz) /256 /duty_target * (prescale+1)
sigma_delta_set_prescale_target( prescale, duty );
}
void platform_sigma_delta_set_prescale( uint8_t prescale )
{
sigma_delta_set_prescale_target( prescale, -1 );
}
void platform_sigma_delta_set_target( uint8_t target )
{
sigma_delta_set_prescale_target( -1, target );
}
// *****************************************************************************
// I2C platform interface
......@@ -473,7 +696,7 @@ spi_data_type platform_spi_send_recv( uint8_t id, uint8_t bitlen, spi_data_type
return spi_mast_get_miso( id, 0, bitlen );
}
int platform_spi_set_mosi( uint8_t id, uint8_t offset, uint8_t bitlen, spi_data_type data )
int platform_spi_set_mosi( uint8_t id, uint16_t offset, uint8_t bitlen, spi_data_type data )
{
if (offset + bitlen > 512)
return PLATFORM_ERR;
......@@ -483,7 +706,7 @@ int platform_spi_set_mosi( uint8_t id, uint8_t offset, uint8_t bitlen, spi_data_
return PLATFORM_OK;
}
spi_data_type platform_spi_get_miso( uint8_t id, uint8_t offset, uint8_t bitlen )
spi_data_type platform_spi_get_miso( uint8_t id, uint16_t offset, uint8_t bitlen )
{
if (offset + bitlen > 512)
return 0;
......
......@@ -7,6 +7,8 @@
#include "c_types.h"
#include "driver/pwm.h"
#include "task/task.h"
// Error / status codes
enum
{
......@@ -30,19 +32,26 @@ uint8_t platform_key_led( uint8_t level);
#define PLATFORM_GPIO_INT 2
#define PLATFORM_GPIO_OUTPUT 1
#define PLATFORM_GPIO_OPENDRAIN 3
#define PLATFORM_GPIO_INPUT 0
#define PLATFORM_GPIO_HIGH 1
#define PLATFORM_GPIO_LOW 0
/* GPIO interrupt handler */
typedef void (* platform_gpio_intr_handler_fn_t)( unsigned pin, unsigned level );
typedef uint32_t (* platform_hook_function)(uint32_t bitmask);
static inline int platform_gpio_exists( unsigned pin ) { return pin < NUM_GPIO; }
int platform_gpio_mode( unsigned pin, unsigned mode, unsigned pull );
int platform_gpio_write( unsigned pin, unsigned level );
int platform_gpio_read( unsigned pin );
void platform_gpio_init( platform_gpio_intr_handler_fn_t cb );
int platform_gpio_intr_init( unsigned pin, GPIO_INT_TYPE type );
// Note that these functions will not be compiled in unless GPIO_INTERRUPT_ENABLE and
// GPIO_INTERRUPT_HOOK_ENABLE are defined.
int platform_gpio_register_intr_hook(uint32_t gpio_bits, platform_hook_function hook);
#define platform_gpio_unregister_intr_hook(hook) \
platform_gpio_register_intr_hook(0, hook);
void platform_gpio_intr_init( unsigned pin, GPIO_INT_TYPE type );
void platform_gpio_init( task_handle_t gpio_task );
// *****************************************************************************
// Timer subsection
......@@ -62,7 +71,7 @@ enum
ELUA_CAN_ID_EXT
};
int platform_can_exists( unsigned id );
static inline int platform_can_exists( unsigned id ) { return NUM_CAN && (id < NUM_CAN); }
uint32_t platform_can_setup( unsigned id, uint32_t clock );
int platform_can_send( unsigned id, uint32_t canid, uint8_t idtype, uint8_t len, const uint8_t *data );
int platform_can_recv( unsigned id, uint32_t *canid, uint8_t *idtype, uint8_t *len, uint8_t *data );
......@@ -95,14 +104,14 @@ int platform_can_recv( unsigned id, uint32_t *canid, uint8_t *idtype, uint8_t *l
typedef uint32_t spi_data_type;
// The platform SPI functions
int platform_spi_exists( unsigned id );
static inline int platform_spi_exists( unsigned id ) { return id < NUM_SPI; }
uint32_t platform_spi_setup( uint8_t id, int mode, unsigned cpol, unsigned cpha, uint32_t clock_div);
int platform_spi_send( uint8_t id, uint8_t bitlen, spi_data_type data );
spi_data_type platform_spi_send_recv( uint8_t id, uint8_t bitlen, spi_data_type data );
void platform_spi_select( unsigned id, int is_select );
int platform_spi_set_mosi( uint8_t id, uint8_t offset, uint8_t bitlen, spi_data_type data );
spi_data_type platform_spi_get_miso( uint8_t id, uint8_t offset, uint8_t bitlen );
int platform_spi_set_mosi( uint8_t id, uint16_t offset, uint8_t bitlen, spi_data_type data );
spi_data_type platform_spi_get_miso( uint8_t id, uint16_t offset, uint8_t bitlen );
int platform_spi_transaction( uint8_t id, uint8_t cmd_bitlen, spi_data_type cmd_data,
uint8_t addr_bitlen, spi_data_type addr_data,
uint16_t mosi_bitlen, uint8_t dummy_bitlen, int16_t miso_bitlen );
......@@ -140,7 +149,7 @@ enum
#define PLATFORM_UART_FLOW_CTS 2
// The platform UART functions
int platform_uart_exists( unsigned id );
static inline int platform_uart_exists( unsigned id ) { return id < NUM_UART; }
uint32_t platform_uart_setup( unsigned id, uint32_t baud, int databits, int parity, int stopbits );
int platform_uart_set_buffer( unsigned id, unsigned size );
void platform_uart_send( unsigned id, uint8_t data );
......@@ -149,6 +158,7 @@ int platform_uart_recv( unsigned id, unsigned timer_id, timer_data_type timeout
int platform_s_uart_recv( unsigned id, timer_data_type timeout );
int platform_uart_set_flow_control( unsigned id, int type );
int platform_s_uart_set_flow_control( unsigned id, int type );
void platform_uart_alt( int set );
// *****************************************************************************
// PWM subsection
......@@ -162,10 +172,11 @@ int platform_s_uart_set_flow_control( unsigned id, int type );
#define DUTY(d) ((uint16_t)( ((unsigned)(d)*PWM_DEPTH) / NORMAL_PWM_DEPTH) )
// The platform PWM functions
int platform_pwm_exists( unsigned id );
void platform_pwm_init( void );
static inline int platform_pwm_exists( unsigned id ) { return ((id < NUM_PWM) && (id > 0)); }
uint32_t platform_pwm_setup( unsigned id, uint32_t frequency, unsigned duty );
void platform_pwm_close( unsigned id );
void platform_pwm_start( unsigned id );
bool platform_pwm_start( unsigned id );
void platform_pwm_stop( unsigned id );
uint32_t platform_pwm_set_clock( unsigned id, uint32_t data );
uint32_t platform_pwm_get_clock( unsigned id );
......@@ -184,7 +195,7 @@ uint32_t platform_adc_set_clock( unsigned id, uint32_t frequency);
int platform_adc_check_timer_id( unsigned id, unsigned timer_id );
// ADC Common Functions
int platform_adc_exists( unsigned id );
static inline int platform_adc_exists( unsigned id ) { return id < NUM_ADC; }
uint32_t platform_adc_get_maxval( unsigned id );
uint32_t platform_adc_set_smoothing( unsigned id, uint32_t length );
void platform_adc_set_blocking( unsigned id, uint32_t mode );
......@@ -192,6 +203,29 @@ void platform_adc_set_freerunning( unsigned id, uint32_t mode );
uint32_t platform_adc_is_done( unsigned id );
void platform_adc_set_timer( unsigned id, uint32_t timer );
// ****************************************************************************
// OneWire functions
static inline int platform_ow_exists( unsigned id ) { return ((id < NUM_OW) && (id > 0)); }
// ****************************************************************************
// Timer functions
static inline int platform_tmr_exists( unsigned id ) { return id < NUM_TMR; }
// *****************************************************************************
// Sigma-Delta platform interface
// ****************************************************************************
// Sigma-Delta functions
static inline int platform_sigma_delta_exists( unsigned id ) {return ((id < NUM_GPIO) && (id > 0)); }
uint8_t platform_sigma_delta_setup( uint8_t pin );
uint8_t platform_sigma_delta_close( uint8_t pin );
void platform_sigma_delta_set_pwmduty( uint8_t duty );
void platform_sigma_delta_set_prescale( uint8_t prescale );
void platform_sigma_delta_set_target( uint8_t target );
// *****************************************************************************
// I2C platform interface
......@@ -209,7 +243,11 @@ enum
PLATFORM_I2C_DIRECTION_RECEIVER
};
int platform_i2c_exists( unsigned id );
#ifdef NUM_I2C
static inline int platform_i2c_exists( unsigned id ) { return id < NUM_I2C; }
#else
static inline int platform_i2c_exists( unsigned id ) { return 0; }
#endif
uint32_t platform_i2c_setup( unsigned id, uint8_t sda, uint8_t scl, uint32_t speed );
void platform_i2c_send_start( unsigned id );
void platform_i2c_send_stop( unsigned id );
......@@ -253,6 +291,14 @@ uint32_t platform_flash_mapped2phys (uint32_t mapped_addr);
void* platform_get_first_free_ram( unsigned id );
void* platform_get_last_free_ram( unsigned id );
// *****************************************************************************
// Other glue
int platform_ow_exists( unsigned id );
int platform_gpio_exists( unsigned id );
int platform_tmr_exists( unsigned id );
// *****************************************************************************
// Helper macros
#define MOD_CHECK_ID( mod, id )\
......@@ -262,7 +308,7 @@ void* platform_get_last_free_ram( unsigned id );
#define MOD_CHECK_TIMER( id )\
if( id == PLATFORM_TIMER_SYS_ID && !platform_timer_sys_available() )\
return luaL_error( L, "the system timer is not available on this platform" );\
if( !platform_timer_exists( id ) )\
if( !platform_tmr_exists( id ) )\
return luaL_error( L, "timer %d does not exist", ( unsigned )id )\
#define MOD_CHECK_RES_ID( mod, id, resmod, resid )\
......
......@@ -499,7 +499,7 @@ void smart_end(){
wifi_station_connect();
os_timer_disarm(&smart_timer);
os_timer_setfn(&smart_timer, (os_timer_func_t *)station_check_connect, 1);
os_timer_setfn(&smart_timer, (os_timer_func_t *)station_check_connect, (void *)1);
os_timer_arm(&smart_timer, STATION_CHECK_TIME, 0); // no repeat
}
}
......@@ -716,6 +716,6 @@ void station_check_connect(bool smart){
break;
}
os_timer_disarm(&smart_timer);
os_timer_setfn(&smart_timer, (os_timer_func_t *)station_check_connect, smart);
os_timer_setfn(&smart_timer, (os_timer_func_t *)station_check_connect, (void *)(int)smart);
os_timer_arm(&smart_timer, STATION_CHECK_TIME, 0); // no repeat
}
......@@ -571,6 +571,7 @@ void myspiffs_clearerr( int fd );
int myspiffs_check( void );
int myspiffs_rename( const char *old, const char *newname );
size_t myspiffs_size( int fd );
int myspiffs_format (void);
s32_t SPIFFS_eof(spiffs *fs, spiffs_file fh);
s32_t SPIFFS_tell(spiffs *fs, spiffs_file fh);
......
......@@ -13,12 +13,8 @@
#include "c_stdint.h"
#include "c_string.h"
typedef sint32_t s32_t;
typedef uint32_t u32_t;
typedef sint16_t s16_t;
typedef uint16_t u16_t;
typedef sint8_t s8_t;
typedef uint8_t u8_t;
// For u32_t etc
#include "user_interface.h"
// compile time switches
......
......@@ -250,6 +250,10 @@ s32_t spiffs_gc_find_candidate(
// divide up work area into block indices and scores
// todo alignment?
// YES DO PROPER ALIGNMENT !^@#%!@%!
if (max_candidates & 1)
++max_candidates; // HACK WORKAROUND ICK for sizeof(spiffs_block_idx)==2
spiffs_block_ix *cand_blocks = (spiffs_block_ix *)fs->work;
s32_t *cand_scores = (s32_t *)(fs->work + max_candidates * sizeof(spiffs_block_ix));
......
......@@ -764,7 +764,8 @@ static s32_t spiffs_read_dir_v(
(SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_IXDELE)) {
struct spiffs_dirent *e = (struct spiffs_dirent *)user_p;
e->obj_id = obj_id;
strcpy((char *)e->name, (char *)objix_hdr.name);
strncpy((char *)e->name, (char *)objix_hdr.name, SPIFFS_OBJ_NAME_LEN);
e->type = objix_hdr.type;
e->size = objix_hdr.size == SPIFFS_UNDEFINED_LEN ? 0 : objix_hdr.size;
e->pix = pix;
......
......@@ -1349,7 +1349,7 @@ static s32_t spiffs_object_find_object_index_header_by_name_v(
if (objix_hdr.p_hdr.span_ix == 0 &&
(objix_hdr.p_hdr.flags & (SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_IXDELE)) ==
(SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_IXDELE)) {
if (strcmp((char *)user_p, (char *)objix_hdr.name) == 0) {
if (strncmp((char *)user_p, (char *)objix_hdr.name, SPIFFS_OBJ_NAME_LEN) == 0) {
return SPIFFS_OK;
}
}
......@@ -1715,7 +1715,7 @@ static s32_t spiffs_obj_lu_find_free_obj_id_bitmap_v(spiffs *fs, spiffs_obj_id i
if (objix_hdr.p_hdr.span_ix == 0 &&
(objix_hdr.p_hdr.flags & (SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_IXDELE)) ==
(SPIFFS_PH_FLAG_DELET | SPIFFS_PH_FLAG_IXDELE)) {
if (strcmp((char *)user_p, (char *)objix_hdr.name) == 0) {
if (strncmp((char *)user_p, (char *)objix_hdr.name, SPIFFS_OBJ_NAME_LEN) == 0) {
return SPIFFS_ERR_CONFLICTING_NAME;
}
}
......@@ -1745,7 +1745,7 @@ static s32_t spiffs_obj_lu_find_free_obj_id_compact_v(spiffs *fs, spiffs_obj_id
((objix_hdr.p_hdr.flags & (SPIFFS_PH_FLAG_INDEX | SPIFFS_PH_FLAG_FINAL | SPIFFS_PH_FLAG_DELET)) ==
(SPIFFS_PH_FLAG_DELET))) {
// ok object look up entry
if (state->conflicting_name && strcmp((const char *)state->conflicting_name, (char *)objix_hdr.name) == 0) {
if (state->conflicting_name && strncmp((const char *)state->conflicting_name, (char *)objix_hdr.name, SPIFFS_OBJ_NAME_LEN) == 0) {
return SPIFFS_ERR_CONFLICTING_NAME;
}
......
......@@ -12,12 +12,9 @@
# a generated lib/image xxx.a ()
#
ifndef PDIR
GEN_LIBS = libjson.a
GEN_LIBS = libtask.a
endif
#############################################################
# Configuration i.e. compile options etc.
# Target specific stuff (defines etc.) goes in here!
......@@ -41,6 +38,7 @@ endif
INCLUDES := $(INCLUDES) -I $(PDIR)include
INCLUDES += -I ./
INCLUDES += -I ../libc
PDIR := ../$(PDIR)
sinclude $(PDIR)Makefile
/**
This file encapsulates the SDK-based task handling for the NodeMCU Lua firmware.
*/
#include "task/task.h"
#include "mem.h"
#include "c_stdio.h"
#define TASK_HANDLE_MONIKER 0x68680000
#define TASK_HANDLE_MASK 0xFFF80000
#define TASK_HANDLE_UNMASK (~TASK_HANDLE_MASK)
#define TASK_HANDLE_SHIFT 2
#define TASK_HANDLE_ALLOCATION_BRICK 4 // must be a power of 2
#define TASK_DEFAULT_QUEUE_LEN 8
#define TASK_PRIORITY_MASK 3
#define CHECK(p,v,msg) if (!(p)) { NODE_DBG ( msg ); return (v); }
/*
* Private arrays to hold the 3 event task queues and the dispatch callbacks
*/
LOCAL os_event_t *task_Q[TASK_PRIORITY_COUNT];
LOCAL task_callback_t *task_func;
LOCAL int task_count;
LOCAL void task_dispatch (os_event_t *e) {
task_handle_t handle = e->sig;
if ( (handle & TASK_HANDLE_MASK) == TASK_HANDLE_MONIKER) {
uint16 entry = (handle & TASK_HANDLE_UNMASK) >> TASK_HANDLE_SHIFT;
uint8 priority = handle & TASK_PRIORITY_MASK;
if ( priority <= TASK_PRIORITY_HIGH && task_func && entry < task_count ){
/* call the registered task handler with the specified parameter and priority */
task_func[entry](e->par, priority);
return;
}
}
/* Invalid signals are ignored */
NODE_DBG ( "Invalid signal issued: %08x", handle);
}
/*
* Initialise the task handle callback for a given priority. This doesn't need
* to be called explicitly as the get_id function will call this lazily.
*/
bool task_init_handler(uint8 priority, uint8 qlen) {
if (priority <= TASK_PRIORITY_HIGH && task_Q[priority] == NULL) {
task_Q[priority] = (os_event_t *) os_malloc( sizeof(os_event_t)*qlen );
os_memset (task_Q[priority], 0, sizeof(os_event_t)*qlen);
if (task_Q[priority]) {
return system_os_task( task_dispatch, priority, task_Q[priority], qlen );
}
}
return false;
}
task_handle_t task_get_id(task_callback_t t) {
int p = TASK_PRIORITY_COUNT;
/* Initialise and uninitialised Qs with the default Q len */
while(p--) if (!task_Q[p]) {
CHECK(task_init_handler( p, TASK_DEFAULT_QUEUE_LEN ), 0, "Task initialisation failed");
}
if ( (task_count & (TASK_HANDLE_ALLOCATION_BRICK - 1)) == 0 ) {
/* With a brick size of 4 this branch is taken at 0, 4, 8 ... and the new size is +4 */
task_func =(task_callback_t *) os_realloc(task_func,
sizeof(task_callback_t)*(task_count+TASK_HANDLE_ALLOCATION_BRICK));
CHECK(task_func, 0 , "Malloc failure in task_get_id");
os_memset (task_func+task_count, 0, sizeof(task_callback_t)*TASK_HANDLE_ALLOCATION_BRICK);
}
task_func[task_count++] = t;
return TASK_HANDLE_MONIKER + ((task_count-1) << TASK_HANDLE_SHIFT);
}
......@@ -15,6 +15,7 @@ ifndef PDIR
GEN_LIBS = tsl2561lib.a
endif
STD_CFLAGS=-std=gnu11 -Wimplicit
#############################################################
# Configuration i.e. compile options etc.
......
......@@ -15,6 +15,8 @@ ifndef PDIR
GEN_LIBS = u8glib.a
endif
STD_CFLAGS=-std=gnu11 -Wimplicit
#############################################################
# Configuration i.e. compile options etc.
# Target specific stuff (defines etc.) goes in here!
......
......@@ -1163,6 +1163,7 @@ struct _u8g_t
u8g_box_t current_page; /* current box of the visible page */
uint8_t i2c_addr;
uint8_t use_delay;
};
#define u8g_GetFontAscent(u8g) ((u8g)->font_ref_ascent)
......@@ -1523,7 +1524,7 @@ const char *u8g_u16toa(uint16_t v, uint8_t d);
/* u8g_delay.c */
/* delay by the specified number of milliseconds */
void u8g_Delay(uint16_t val);
void u8g_Delay(u8g_t *u8g, uint16_t val);
/* delay by one microsecond */
void u8g_MicroDelay(void);
......
......@@ -151,9 +151,9 @@ uint8_t u8g_WriteEscSeqP(u8g_t *u8g, u8g_dev_t *dev, const uint8_t *esc_seq)
value &= 0x0f;
value <<= 4;
value+=2;
u8g_Delay(value);
u8g_Delay(u8g, value);
u8g_SetResetHigh(u8g, dev);
u8g_Delay(value);
u8g_Delay(u8g, value);
}
else if ( value >= 0xbe )
{
......@@ -162,7 +162,7 @@ uint8_t u8g_WriteEscSeqP(u8g_t *u8g, u8g_dev_t *dev, const uint8_t *esc_seq)
}
else if ( value <= 127 )
{
u8g_Delay(value);
u8g_Delay(u8g, value);
}
is_escape = 0;
}
......
......@@ -71,7 +71,7 @@
# define USE_AVR_DELAY
#elif defined(__18CXX)
# define USE_PIC18_DELAY
#elif defined(__arm__)
#elif defined(__arm__) || defined(__XTENSA__)
/* do not define anything, all procedures are expected to be defined outside u8glib */
/*
......
......@@ -78,7 +78,7 @@ uint8_t u8g_dev_a2_micro_printer_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, voi
u8g_WriteByte(u8g, dev, *ptr);
ptr++;
}
u8g_Delay(LINE_DELAY);
u8g_Delay(u8g, LINE_DELAY);
y++;
}
......@@ -160,7 +160,7 @@ uint8_t u8g_dev_a2_micro_printer_double_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t m
u8g_WriteByte(u8g, dev, u8g_dev_expand4(*p2 & 15));
p2++;
}
u8g_Delay(LINE_DELAY);
u8g_Delay(u8g, LINE_DELAY);
p2 = ptr;
for( j = 0; j < pb->width/8; j++ )
{
......@@ -168,7 +168,7 @@ uint8_t u8g_dev_a2_micro_printer_double_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t m
u8g_WriteByte(u8g, dev, u8g_dev_expand4(*p2 & 15));
p2++;
}
u8g_Delay(LINE_DELAY);
u8g_Delay(u8g, LINE_DELAY);
ptr += pb->width/8;
y++;
}
......
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