Commit 711a537c authored by markusgritsch's avatar markusgritsch
Browse files

Merge pull request #1 from nodemcu/dev

Dev
parents 378398d4 0f6046d8
/*
u8g_dev_ssd1322_nhd31oled_bw.c
1-Bit (BW) Driver for SSD1322 Controller (OLED Display)
Tested with NHD-3.12-25664
Universal 8bit Graphics Library
Copyright (c) 2012, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
SSD130x Monochrom OLED Controller
SSD131x Character OLED Controller
SSD132x Graylevel OLED Controller
SSD1331 Color OLED Controller
*/
#include "u8g.h"
/* width must be multiple of 8, largest value is 248 unless u8g 16 bit mode is enabled */
#if defined(U8G_16BIT)
#define WIDTH 256
#else
#define WIDTH 248
#endif
#define HEIGHT 64
#define PAGE_HEIGHT 8
/*
http://www.newhavendisplay.com/app_notes/OLED_25664.txt
http://www.newhavendisplay.com/forum/viewtopic.php?f=15&t=3758
*/
static const uint8_t u8g_dev_ssd1322_1bit_nhd_312_init_seq[] PROGMEM = {
U8G_ESC_DLY(10), /* delay 10 ms */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_ADR(0), /* instruction mode */
0x0fd, /* lock command */
U8G_ESC_ADR(1), /* data mode */
0x012, /* unlock */
U8G_ESC_ADR(0), /* instruction mode */
0x0ae, /* display off, sleep mode */
U8G_ESC_ADR(0), /* instruction mode */
0x0b3,
U8G_ESC_ADR(1), /* data mode */
0x091, /* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec) */
U8G_ESC_ADR(0), /* instruction mode */
0x0ca, /* multiplex ratio */
U8G_ESC_ADR(1), /* data mode */
0x03f, /* 1/64 Duty (0x0F~0x3F) */
U8G_ESC_ADR(0), /* instruction mode */
0x0a2,
U8G_ESC_ADR(1), /* data mode */
0x000, /* display offset, shift mapping ram counter */
U8G_ESC_ADR(0), /* instruction mode */
0x0a1,
U8G_ESC_ADR(1), /* data mode */
0x000, /* display start line */
U8G_ESC_ADR(0), /* instruction mode */
0x0a0, /* Set Re-Map / Dual COM Line Mode */
U8G_ESC_ADR(1), /* data mode */
0x014, /* was 0x014 */
0x011, /* was 0x011 */
U8G_ESC_ADR(0), /* instruction mode */
0x0ab,
U8G_ESC_ADR(1), /* data mode */
0x001, /* Enable Internal VDD Regulator */
U8G_ESC_ADR(0), /* instruction mode */
0x0b4, /* Display Enhancement A */
U8G_ESC_ADR(1), /* data mode */
0x0a0,
0x005|0x0fd,
U8G_ESC_ADR(0), /* instruction mode */
0x0c1, /* contrast */
U8G_ESC_ADR(1), /* data mode */
0x09f,
U8G_ESC_ADR(0), /* instruction mode */
0x0c7, /* Set Scale Factor of Segment Output Current Control */
U8G_ESC_ADR(1), /* data mode */
0x00f,
U8G_ESC_ADR(0), /* instruction mode */
0x0b9, /* linear gray scale */
U8G_ESC_ADR(0), /* instruction mode */
0x0b1, /* Phase 1 (Reset) & Phase 2 (Pre-Charge) Period Adjustment */
U8G_ESC_ADR(1), /* data mode */
0x0e2,
U8G_ESC_ADR(0), /* instruction mode */
0x0d1, /* Display Enhancement B */
U8G_ESC_ADR(1), /* data mode */
0x082|0x020,
0x020,
U8G_ESC_ADR(0), /* instruction mode */
0x0bb, /* precharge voltage */
U8G_ESC_ADR(1), /* data mode */
0x01f,
U8G_ESC_ADR(0), /* instruction mode */
0x0b6, /* precharge period */
U8G_ESC_ADR(1), /* data mode */
0x008,
U8G_ESC_ADR(0), /* instruction mode */
0x0be, /* vcomh */
U8G_ESC_ADR(1), /* data mode */
0x007,
U8G_ESC_ADR(0), /* instruction mode */
0x0a6, /* normal display */
U8G_ESC_ADR(0), /* instruction mode */
0x0a9, /* exit partial display */
U8G_ESC_ADR(0), /* instruction mode */
0x0af, /* display on */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_ssd1322_1bit_nhd_312_prepare_page_seq[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x015, /* column address... */
U8G_ESC_ADR(1), /* data mode */
0x01c, /* start at column 0 */
0x05b, /* end column */
U8G_ESC_ADR(0), /* instruction mode */
0x075, /* row address... */
U8G_ESC_ADR(1), /* data mode */
U8G_ESC_END /* end of sequence */
};
static void u8g_dev_ssd1322_1bit_prepare_row(u8g_t *u8g, u8g_dev_t *dev, uint8_t delta_row)
{
uint8_t row = ((u8g_pb_t *)(dev->dev_mem))->p.page;
row *= ((u8g_pb_t *)(dev->dev_mem))->p.page_height;
row += delta_row;
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1322_1bit_nhd_312_prepare_page_seq);
u8g_WriteByte(u8g, dev, row); /* start at the selected row */
u8g_WriteByte(u8g, dev, row+1); /* end within the selected row */
u8g_SetAddress(u8g, dev, 0); /* instruction mode mode */
u8g_WriteByte(u8g, dev, 0x05c); /* write to ram */
u8g_SetAddress(u8g, dev, 1); /* data mode */
}
static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0ae, /* display off */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0af, /* display on */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
uint8_t u8g_dev_ssd1322_nhd31oled_bw_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1322_1bit_nhd_312_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t i;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
uint8_t *p = pb->buf;
u8g_uint_t cnt;
cnt = pb->width;
cnt >>= 3;
for( i = 0; i < pb->p.page_height; i++ )
{
u8g_dev_ssd1322_1bit_prepare_row(u8g, dev, i); /* this will also enable chip select */
#if !defined(U8G_16BIT)
u8g_WriteByte(u8g, dev, 0x0ff);
u8g_WriteByte(u8g, dev, 0x0ff);
#endif
u8g_WriteSequenceBWTo16GrDevice(u8g, dev, cnt, p);
#if !defined(U8G_16BIT)
u8g_WriteByte(u8g, dev, 0x0ff);
u8g_WriteByte(u8g, dev, 0x0ff);
#endif
u8g_MicroDelay(); // for DUE?
u8g_SetChipSelect(u8g, dev, 0);
p+=cnt;
}
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
u8g_MicroDelay(); // for DUE?
u8g_SetChipSelect(u8g, dev, 0);
break;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
return 1;
}
return u8g_dev_pb8h1_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_ssd1322_nhd31oled_2x_bw_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1322_1bit_nhd_312_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t i;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
uint8_t *p = pb->buf;
u8g_uint_t cnt;
cnt = pb->width;
cnt >>= 3;
for( i = 0; i < pb->p.page_height; i++ )
{
u8g_dev_ssd1322_1bit_prepare_row(u8g, dev, i); /* this will also enable chip select */
#if !defined(U8G_16BIT)
u8g_WriteByte(u8g, dev, 0x0ff);
u8g_WriteByte(u8g, dev, 0x0ff);
#endif
u8g_WriteSequenceBWTo16GrDevice(u8g, dev, cnt, p);
#if !defined(U8G_16BIT)
u8g_WriteByte(u8g, dev, 0x0ff);
u8g_WriteByte(u8g, dev, 0x0ff);
#endif
u8g_MicroDelay(); // for DUE?
u8g_SetChipSelect(u8g, dev, 0);
p+=cnt;
}
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x0c1); /* 21 May 2013, fixed contrast command */
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
u8g_SetChipSelect(u8g, dev, 0);
break;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
return 1;
}
return u8g_dev_pb16h1_base_fn(u8g, dev, msg, arg);
}
U8G_PB_DEV(u8g_dev_ssd1322_nhd31oled_bw_sw_spi , WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1322_nhd31oled_bw_fn, U8G_COM_SW_SPI);
U8G_PB_DEV(u8g_dev_ssd1322_nhd31oled_bw_hw_spi , WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1322_nhd31oled_bw_fn, U8G_COM_HW_SPI);
U8G_PB_DEV(u8g_dev_ssd1322_nhd31oled_bw_parallel , WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1322_nhd31oled_bw_fn, U8G_COM_FAST_PARALLEL);
#define DWIDTH (WIDTH*2)
uint8_t u8g_dev_ssd1322_nhd31oled_2x_bw_buf[DWIDTH] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_ssd1322_nhd31oled_2x_bw_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1322_nhd31oled_2x_bw_buf};
u8g_dev_t u8g_dev_ssd1322_nhd31oled_2x_bw_sw_spi = { u8g_dev_ssd1322_nhd31oled_2x_bw_fn, &u8g_dev_ssd1322_nhd31oled_2x_bw_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_ssd1322_nhd31oled_2x_bw_hw_spi = { u8g_dev_ssd1322_nhd31oled_2x_bw_fn, &u8g_dev_ssd1322_nhd31oled_2x_bw_pb, U8G_COM_HW_SPI };
/*
u8g_dev_ssd1322_nhd31oled_gr.c
2-Bit (4L) Driver for SSD1322 Controller (OLED Display)
Tested with NHD-3.12-25664
Universal 8bit Graphics Library
Copyright (c) 2012, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
SSD130x Monochrom OLED Controller
SSD131x Character OLED Controller
SSD132x Graylevel OLED Controller
SSD1331 Color OLED Controller
*/
#include "u8g.h"
/* width must be multiple of 8, largest value is 248 unless u8g 16 bit mode is enabled */
#if defined(U8G_16BIT)
#define WIDTH 256
#else
#define WIDTH 248
#endif
#define HEIGHT 64
//#define PAGE_HEIGHT 8
/*
http://www.newhavendisplay.com/app_notes/OLED_25664.txt
http://www.newhavendisplay.com/forum/viewtopic.php?f=15&t=3758
*/
static const uint8_t u8g_dev_ssd1322_2bit_nhd_312_init_seq[] PROGMEM = {
U8G_ESC_DLY(10), /* delay 10 ms */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_ADR(0), /* instruction mode */
0x0fd, /* lock command */
U8G_ESC_ADR(1), /* data mode */
0x012, /* unlock */
U8G_ESC_ADR(0), /* instruction mode */
0x0ae, /* display off, sleep mode */
U8G_ESC_ADR(0), /* instruction mode */
0x0b3,
U8G_ESC_ADR(1), /* data mode */
0x091, /* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec) */
U8G_ESC_ADR(0), /* instruction mode */
0x0ca, /* multiplex ratio */
U8G_ESC_ADR(1), /* data mode */
0x03f, /* 1/64 Duty (0x0F~0x3F) */
U8G_ESC_ADR(0), /* instruction mode */
0x0a2,
U8G_ESC_ADR(1), /* data mode */
0x000, /* display offset, shift mapping ram counter */
U8G_ESC_ADR(0), /* instruction mode */
0x0a1,
U8G_ESC_ADR(1), /* data mode */
0x000, /* display start line */
U8G_ESC_ADR(0), /* instruction mode */
0x0a0, /* Set Re-Map / Dual COM Line Mode */
U8G_ESC_ADR(1), /* data mode */
0x014, /* was 0x014 */
0x011, /* was 0x011 */
U8G_ESC_ADR(0), /* instruction mode */
0x0ab,
U8G_ESC_ADR(1), /* data mode */
0x001, /* Enable Internal VDD Regulator */
U8G_ESC_ADR(0), /* instruction mode */
0x0b4, /* Display Enhancement A */
U8G_ESC_ADR(1), /* data mode */
0x0a0,
0x005|0x0fd,
U8G_ESC_ADR(0), /* instruction mode */
0x0c1, /* contrast */
U8G_ESC_ADR(1), /* data mode */
0x09f,
U8G_ESC_ADR(0), /* instruction mode */
0x0c7, /* Set Scale Factor of Segment Output Current Control */
U8G_ESC_ADR(1), /* data mode */
0x00f,
U8G_ESC_ADR(0), /* instruction mode */
0x0b9, /* linear gray scale */
U8G_ESC_ADR(0), /* instruction mode */
0x0b1, /* Phase 1 (Reset) & Phase 2 (Pre-Charge) Period Adjustment */
U8G_ESC_ADR(1), /* data mode */
0x0e2,
U8G_ESC_ADR(0), /* instruction mode */
0x0d1, /* Display Enhancement B */
U8G_ESC_ADR(1), /* data mode */
0x082|0x020,
0x020,
U8G_ESC_ADR(0), /* instruction mode */
0x0bb, /* precharge voltage */
U8G_ESC_ADR(1), /* data mode */
0x01f,
U8G_ESC_ADR(0), /* instruction mode */
0x0b6, /* precharge period */
U8G_ESC_ADR(1), /* data mode */
0x008,
U8G_ESC_ADR(0), /* instruction mode */
0x0be, /* vcomh */
U8G_ESC_ADR(1), /* data mode */
0x007,
U8G_ESC_ADR(0), /* instruction mode */
0x0a6, /* normal display */
U8G_ESC_ADR(0), /* instruction mode */
0x0a9, /* exit partial display */
U8G_ESC_ADR(0), /* instruction mode */
0x0af, /* display on */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_ssd1322_2bit_nhd_312_prepare_page_seq[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x015, /* column address... */
U8G_ESC_ADR(1), /* data mode */
0x01c, /* start at column 0 */
0x05b, /* end column */
U8G_ESC_ADR(0), /* instruction mode */
0x075, /* row address... */
U8G_ESC_ADR(1), /* data mode */
U8G_ESC_END /* end of sequence */
};
static void u8g_dev_ssd1322_2bit_prepare_row(u8g_t *u8g, u8g_dev_t *dev, uint8_t delta_row)
{
uint8_t row = ((u8g_pb_t *)(dev->dev_mem))->p.page;
row *= ((u8g_pb_t *)(dev->dev_mem))->p.page_height;
row += delta_row;
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1322_2bit_nhd_312_prepare_page_seq);
u8g_WriteByte(u8g, dev, row); /* start at the selected row */
u8g_WriteByte(u8g, dev, row+1); /* end within the selected row */
u8g_SetAddress(u8g, dev, 0); /* instruction mode mode */
u8g_WriteByte(u8g, dev, 0x05c); /* write to ram */
u8g_SetAddress(u8g, dev, 1); /* data mode */
}
static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0ae, /* display off */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0af, /* display on */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
uint8_t u8g_dev_ssd1322_nhd31oled_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1322_2bit_nhd_312_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t i;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
uint8_t *p = pb->buf;
u8g_uint_t cnt;
cnt = pb->width;
cnt >>= 2;
for( i = 0; i < pb->p.page_height; i++ )
{
u8g_dev_ssd1322_2bit_prepare_row(u8g, dev, i); /* this will also enable chip select */
#if !defined(U8G_16BIT)
u8g_WriteByte(u8g, dev, 0x00);
u8g_WriteByte(u8g, dev, 0x00);
#endif
u8g_WriteSequence4LTo16GrDevice(u8g, dev, cnt, p);
#if !defined(U8G_16BIT)
u8g_WriteByte(u8g, dev, 0x00);
u8g_WriteByte(u8g, dev, 0x00);
#endif
u8g_MicroDelay(); // for DUE?
u8g_SetChipSelect(u8g, dev, 0);
p+=cnt;
}
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
u8g_MicroDelay(); // for DUE?
u8g_SetChipSelect(u8g, dev, 0);
break;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
return 1;
}
return u8g_dev_pb8h2_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_ssd1322_nhd31oled_2x_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1322_2bit_nhd_312_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t i;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
uint8_t *p = pb->buf;
u8g_uint_t cnt;
cnt = pb->width;
cnt >>= 2; /* 23 Oct 2013, changed to 2 */
for( i = 0; i < pb->p.page_height; i++ )
{
u8g_dev_ssd1322_2bit_prepare_row(u8g, dev, i); /* this will also enable chip select */
#if !defined(U8G_16BIT)
u8g_WriteByte(u8g, dev, 0x00);
u8g_WriteByte(u8g, dev, 0x00);
#endif
u8g_WriteSequence4LTo16GrDevice(u8g, dev, cnt, p);
#if !defined(U8G_16BIT)
u8g_WriteByte(u8g, dev, 0x00);
u8g_WriteByte(u8g, dev, 0x00);
#endif
u8g_MicroDelay(); // for DUE?
u8g_SetChipSelect(u8g, dev, 0);
p+=cnt;
}
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
u8g_SetChipSelect(u8g, dev, 0);
break;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
return 1;
}
return u8g_dev_pb16h2_base_fn(u8g, dev, msg, arg);
}
U8G_PB_DEV(u8g_dev_ssd1322_nhd31oled_gr_sw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1322_nhd31oled_gr_fn, U8G_COM_SW_SPI);
U8G_PB_DEV(u8g_dev_ssd1322_nhd31oled_gr_hw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1322_nhd31oled_gr_fn, U8G_COM_HW_SPI);
U8G_PB_DEV(u8g_dev_ssd1322_nhd31oled_gr_parallel , WIDTH, HEIGHT, 4, u8g_dev_ssd1322_nhd31oled_gr_fn, U8G_COM_FAST_PARALLEL);
#define DWIDTH (WIDTH*2)
uint8_t u8g_dev_ssd1322_nhd31oled_2x_gr_buf[DWIDTH] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_ssd1322_nhd31oled_2x_gr_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1322_nhd31oled_2x_gr_buf};
u8g_dev_t u8g_dev_ssd1322_nhd31oled_2x_gr_sw_spi = { u8g_dev_ssd1322_nhd31oled_2x_gr_fn, &u8g_dev_ssd1322_nhd31oled_2x_gr_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_ssd1322_nhd31oled_2x_gr_hw_spi = { u8g_dev_ssd1322_nhd31oled_2x_gr_fn, &u8g_dev_ssd1322_nhd31oled_2x_gr_pb, U8G_COM_HW_SPI };
/*
u8g_dev_ssd1325_nhd27oled_bw.c
1-Bit (BW) Driver for SSD1325 Controller (OLED Display)
Tested with NHD-2.7-12864UCY3
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
SSD130x Monochrom OLED Controller
SSD131x Character OLED Controller
SSD132x Graylevel OLED Controller
SSD1331 Color OLED Controller
*/
#ifdef OBSOLETE_CODE
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 64
#define PAGE_HEIGHT 8
/* http://www.newhavendisplay.com/app_notes/OLED_2_7_12864.txt */
static const uint8_t u8g_dev_ssd1325_1bit_nhd_27_12864ucy3_init_seq[] PROGMEM = {
U8G_ESC_DLY(10), /* delay 10 ms */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
0x0ae, /* display off, sleep mode */
0x0b3, 0x091, /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
0x0a8, 0x03f, /* multiplex ratio: 0x03f * 1/64 duty */
0x0a2, 0x04c, /* display offset, shift mapping ram counter */
0x0a1, 0x000, /* display start line */
0x0ad, 0x002, /* master configuration: disable embedded DC-DC, enable internal VCOMH */
0x0a0, 0x056, /* remap configuration, vertical address increment, enable nibble remap (upper nibble is left) */
0x086, /* full current range (0x084, 0x085, 0x086) */
0x0b8, /* set gray scale table */
0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x065, 0x076,
0x081, 0x070, /* contrast, brightness, 0..128, Newhaven: 0x040 */
0x0b2, 0x051, /* frame frequency (row period) */
0x0b1, 0x055, /* phase length */
0x0bc, 0x010, /* pre-charge voltage level */
0x0b4, 0x002, /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0b0, 0x028, /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0be, 0x01c, /* VCOMH voltage */
0x0bf, 0x002|0x00d, /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0a5, /* all pixel on */
0x0af, /* display on */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a4, /* normal display mode */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_ssd1325_1bit_nhd_27_12864ucy3_prepare_page_seq[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x015, /* column address... */
0x000, /* start at column 0 */
0x03f, /* end at column 63 (which is y == 127), because there are two pixel in one column */
0x075, /* row address... */
U8G_ESC_END /* end of sequence */
};
static void u8g_dev_ssd1325_1bit_prepare_page(u8g_t *u8g, u8g_dev_t *dev)
{
uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_1bit_nhd_27_12864ucy3_prepare_page_seq);
page <<= 3;
u8g_WriteByte(u8g, dev, page); /* start at the selected page */
page += 7;
u8g_WriteByte(u8g, dev, page); /* end within the selected page */
u8g_SetAddress(u8g, dev, 1); /* data mode */
}
static void u8g_dev_ssd1325_1bit_2x_prepare_page(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
{
uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_1bit_nhd_27_12864ucy3_prepare_page_seq);
page <<= 1;
page += is_odd;
page <<= 3;
u8g_WriteByte(u8g, dev, page); /* start at the selected page */
page += 7;
u8g_WriteByte(u8g, dev, page); /* end within the selected page */
u8g_SetAddress(u8g, dev, 1); /* data mode */
}
/* assumes row autoincrement and activated nibble remap */
#ifdef OLD
static void _OLD_u8g_dev_ssd1325_1bit_write_16_pixel(u8g_t *u8g, u8g_dev_t *dev, uint8_t left, uint8_t right)
{
uint8_t d, cnt;
cnt = 8;
do
{
d = 0;
if ( left & 1 )
d |= 0x0f0;
if ( right & 1 )
d |= 0x00f;
u8g_WriteByte(u8g, dev, d);
left >>= 1;
right >>= 1;
cnt--;
}while ( cnt > 0 );
}
#endif
static void u8g_dev_ssd1325_1bit_write_16_pixel(u8g_t *u8g, u8g_dev_t *dev, uint8_t left, uint8_t right)
{
uint8_t d, cnt;
static uint8_t buf[8];
cnt = 8;
do
{
d = 0;
if ( left & 128 )
d |= 0x0f0;
if ( right & 128 )
d |= 0x00f;
cnt--;
buf[cnt] = d;
left <<= 1;
right <<= 1;
}while ( cnt > 0 );
u8g_WriteSequence(u8g, dev, 8, buf);
}
static void u8g_dev_ssd1325_1bit_write_buffer(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
{
uint8_t cnt, left, right;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
ptr = pb->buf;
cnt = pb->width;
if ( is_odd )
ptr += cnt;
cnt >>= 1;
do
{
left = *ptr++;
right = *ptr++;
u8g_dev_ssd1325_1bit_write_16_pixel(u8g, dev, left, right);
cnt--;
} while( cnt > 0 );
}
uint8_t u8g_dev_ssd1325_nhd27oled_bw_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_1bit_nhd_27_12864ucy3_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_dev_ssd1325_1bit_prepare_page(u8g, dev);
u8g_dev_ssd1325_1bit_write_buffer(u8g, dev, 0);
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
u8g_SetChipSelect(u8g, dev, 0);
break;
}
return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_ssd1325_nhd27oled_2x_bw_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_1bit_nhd_27_12864ucy3_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_dev_ssd1325_1bit_2x_prepare_page(u8g, dev, 0);
u8g_dev_ssd1325_1bit_write_buffer(u8g, dev, 0);
u8g_dev_ssd1325_1bit_2x_prepare_page(u8g, dev, 1);
u8g_dev_ssd1325_1bit_write_buffer(u8g, dev, 1);
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
u8g_SetChipSelect(u8g, dev, 0);
break;
}
return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
}
/* disabled, see bw_new.c */
/*
U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_bw_sw_spi , WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1325_nhd27oled_bw_fn, U8G_COM_SW_SPI);
U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_bw_hw_spi , WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1325_nhd27oled_bw_fn, U8G_COM_HW_SPI);
U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_bw_parallel , WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1325_nhd27oled_bw_fn, U8G_COM_FAST_PARALLEL);
*/
/*
uint8_t u8g_dev_ssd1325_nhd27oled_2x_bw_buf[WIDTH*2] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_ssd1325_nhd27oled_2x_bw_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1325_nhd27oled_2x_bw_buf};
u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_bw_sw_spi = { u8g_dev_ssd1325_nhd27oled_2x_bw_fn, &u8g_dev_ssd1325_nhd27oled_2x_bw_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_bw_hw_spi = { u8g_dev_ssd1325_nhd27oled_2x_bw_fn, &u8g_dev_ssd1325_nhd27oled_2x_bw_pb, U8G_COM_HW_SPI };
u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_bw_parallel = { u8g_dev_ssd1325_nhd27oled_2x_bw_fn, &u8g_dev_ssd1325_nhd27oled_2x_bw_pb, U8G_COM_FAST_PARALLEL };
*/
#endif
/*
u8g_dev_ssd1325_nhd27oled_bw.c
1-Bit (BW) Driver for SSD1325 Controller (OLED Display)
Horizontal architecture, completly rewritten
Tested with NHD-2.7-12864UCY3
Universal 8bit Graphics Library
Copyright (c) 2012, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
SSD130x Monochrom OLED Controller
SSD131x Character OLED Controller
SSD132x Graylevel OLED Controller
SSD1331 Color OLED Controller
*/
#include "u8g.h"
/* width must be multiple of 8, largest value is 248 unless u8g 16 bit mode is enabled */
#define WIDTH 128
#define HEIGHT 64
/* http://www.newhavendisplay.com/app_notes/OLED_2_7_12864.txt */
static const uint8_t u8g_dev_ssd1325_nhd_27_12864_init_seq[] PROGMEM = {
U8G_ESC_DLY(10), /* delay 10 ms */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
0x0ae, /* display off, sleep mode */
0x0b3, 0x091, /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
0x0a8, 0x03f, /* multiplex ratio: 0x03f * 1/64 duty */
0x0a2, 0x04c, /* display offset, shift mapping ram counter */
0x0a1, 0x000, /* display start line */
0x0ad, 0x002, /* master configuration: disable embedded DC-DC, enable internal VCOMH */
0x0a0, 0x052, /* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1) */
0x086, /* full current range (0x084, 0x085, 0x086) */
0x0b8, /* set gray scale table */
0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x065, 0x076,
0x081, 0x070, /* contrast, brightness, 0..128, Newhaven: 0x040 */
0x0b2, 0x051, /* frame frequency (row period) */
0x0b1, 0x055, /* phase length */
0x0bc, 0x010, /* pre-charge voltage level */
0x0b4, 0x002, /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0b0, 0x028, /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0be, 0x01c, /* VCOMH voltage */
0x0bf, 0x002|0x00d, /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0a4, /* normal display mode */
0x0af, /* display on */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_ssd1325_prepare_row_seq[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x015, /* column address... */
0x000, /* start at column 0 */
0x03f, /* end at column 63 (which is y == 127), because there are two pixel in one column */
0x075, /* row address... */
U8G_ESC_END /* end of sequence */
};
static void u8g_dev_ssd1325_prepare_row(u8g_t *u8g, u8g_dev_t *dev, uint8_t delta_row)
{
uint8_t row = ((u8g_pb_t *)(dev->dev_mem))->p.page;
row *= ((u8g_pb_t *)(dev->dev_mem))->p.page_height;
row += delta_row;
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_prepare_row_seq);
u8g_WriteByte(u8g, dev, row); /* start at the selected row */
u8g_WriteByte(u8g, dev, row+1); /* end within the selected row */
//u8g_SetAddress(u8g, dev, 0); /* instruction mode mode */
//u8g_WriteByte(u8g, dev, 0x05c); /* write to ram */
u8g_SetAddress(u8g, dev, 1); /* data mode */
}
static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0ae, /* display off */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0af, /* display on */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
static uint8_t u8g_dev_ssd1325_nhd27oled_bw_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
//case U8G_DEV_MSG_IS_BBX_INTERSECTION:
// return u8g_pb_IsIntersection((u8g_pb_t *)(dev->dev_mem), (u8g_dev_arg_bbx_t *)arg);
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_nhd_27_12864_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t i;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
uint8_t *p = pb->buf;
u8g_uint_t cnt;
cnt = pb->width;
cnt >>= 3;
for( i = 0; i < pb->p.page_height; i++ )
{
u8g_dev_ssd1325_prepare_row(u8g, dev, i); /* this will also enable chip select */
u8g_WriteSequenceBWTo16GrDevice(u8g, dev, cnt, p);
u8g_SetChipSelect(u8g, dev, 0);
p+=cnt;
}
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
u8g_SetChipSelect(u8g, dev, 0);
break;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
return 1;
}
return u8g_dev_pb8h1_base_fn(u8g, dev, msg, arg);
}
static uint8_t u8g_dev_ssd1325_nhd27oled_2x_bw_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_nhd_27_12864_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t i;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
uint8_t *p = pb->buf;
u8g_uint_t cnt;
cnt = pb->width;
cnt >>= 3;
for( i = 0; i < pb->p.page_height; i++ )
{
u8g_dev_ssd1325_prepare_row(u8g, dev, i); /* this will also enable chip select */
u8g_WriteSequenceBWTo16GrDevice(u8g, dev, cnt, p);
u8g_SetChipSelect(u8g, dev, 0);
p+=cnt;
}
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
u8g_SetChipSelect(u8g, dev, 0);
break;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
return 1;
}
return u8g_dev_pb16h1_base_fn(u8g, dev, msg, arg);
}
U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_bw_sw_spi , WIDTH, HEIGHT, 8, u8g_dev_ssd1325_nhd27oled_bw_fn, U8G_COM_SW_SPI);
U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_bw_hw_spi , WIDTH, HEIGHT, 8, u8g_dev_ssd1325_nhd27oled_bw_fn, U8G_COM_HW_SPI);
U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_bw_parallel , WIDTH, HEIGHT, 8, u8g_dev_ssd1325_nhd27oled_bw_fn, U8G_COM_FAST_PARALLEL);
uint8_t u8g_dev_ssd1325_nhd27oled_2x_bw_buf[WIDTH*2] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_ssd1325_nhd27oled_2x_bw_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1325_nhd27oled_2x_bw_buf};
u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_bw_sw_spi = { u8g_dev_ssd1325_nhd27oled_2x_bw_fn, &u8g_dev_ssd1325_nhd27oled_2x_bw_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_bw_hw_spi = { u8g_dev_ssd1325_nhd27oled_2x_bw_fn, &u8g_dev_ssd1325_nhd27oled_2x_bw_pb, U8G_COM_HW_SPI };
u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_bw_parallel = { u8g_dev_ssd1325_nhd27oled_2x_bw_fn, &u8g_dev_ssd1325_nhd27oled_2x_bw_pb, U8G_COM_FAST_PARALLEL };
/*
u8g_dev_ssd1325_nhd27oled_gr.c
2-Bit (gray level) Driver for SSD1325 Controller (OLED Display)
Tested with NHD-2.7-12864UCY3
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
SSD130x Monochrom OLED Controller
SSD131x Character OLED Controller
SSD132x Graylevel OLED Controller
SSD1331 Color OLED Controller
*/
#ifdef OBSOLETE_CODE
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 64
/* http://www.newhavendisplay.com/app_notes/OLED_2_7_12864.txt */
static const uint8_t u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq[] PROGMEM = {
U8G_ESC_DLY(10), /* delay 10 ms */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
0x0ae, /* display off, sleep mode */
0x0b3, 0x091, /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
0x0a8, 0x03f, /* multiplex ratio: 0x03f * 1/64 duty */
0x0a2, 0x04c, /* display offset, shift mapping ram counter */
0x0a1, 0x000, /* display start line */
0x0ad, 0x002, /* master configuration: disable embedded DC-DC, enable internal VCOMH */
0x0a0, 0x056, /* remap configuration, vertical address increment, enable nibble remap (upper nibble is left) */
0x086, /* full current range (0x084, 0x085, 0x086) */
0x0b8, /* set gray scale table */
//0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x065, 0x076,
0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x077, 0x077, // 4L mode uses 0, 2, 4, 7
0x081, 0x070, /* contrast, brightness, 0..128, Newhaven: 0x040 */
0x0b2, 0x051, /* frame frequency (row period) */
0x0b1, 0x055, /* phase length */
0x0bc, 0x010, /* pre-charge voltage level */
0x0b4, 0x002, /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0b0, 0x028, /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0be, 0x01c, /* VCOMH voltage */
0x0bf, 0x002|0x00d, /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0a5, /* all pixel on */
0x0af, /* display on */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a4, /* normal display mode */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x015, /* column address... */
0x000, /* start at column 0 */
0x03f, /* end at column 63 (which is y == 127), because there are two pixel in one column */
0x075, /* row address... */
U8G_ESC_END /* end of sequence */
};
static void u8g_dev_ssd1325_2bit_prepare_page(u8g_t *u8g, u8g_dev_t *dev)
{
uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq);
page <<= 2;
u8g_WriteByte(u8g, dev, page); /* start at the selected page */
page += 3;
u8g_WriteByte(u8g, dev, page); /* end within the selected page */
u8g_SetAddress(u8g, dev, 1); /* data mode */
}
static void u8g_dev_ssd1325_2bit_2x_prepare_page(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
{
uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq);
page <<= 1;
page += is_odd;
page <<= 2;
u8g_WriteByte(u8g, dev, page); /* start at the selected page */
page += 3;
u8g_WriteByte(u8g, dev, page); /* end within the selected page */
u8g_SetAddress(u8g, dev, 1); /* data mode */
}
/* assumes row autoincrement and activated nibble remap */
static void u8g_dev_ssd1325_2bit_write_4_pixel(u8g_t *u8g, u8g_dev_t *dev, uint8_t left, uint8_t right)
{
uint8_t d, tmp, cnt;
cnt = 4;
do
{
d = left;
d &= 3;
d <<= 4;
tmp = right;
tmp &= 3;
d |= tmp;
d <<= 2;
u8g_WriteByte(u8g, dev, d);
left >>= 2;
right >>= 2;
cnt--;
}while ( cnt > 0 );
}
static void u8g_dev_ssd1325_2bit_write_buffer(u8g_t *u8g, u8g_dev_t *dev)
{
uint8_t cnt, left, right;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
cnt = pb->width;
cnt >>= 1;
ptr = pb->buf;
do
{
left = *ptr++;
right = *ptr++;
u8g_dev_ssd1325_2bit_write_4_pixel(u8g, dev, left, right);
cnt--;
} while( cnt > 0 );
}
static void u8g_dev_ssd1325_2bit_2x_write_buffer(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
{
uint8_t cnt, left, right;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
ptr = pb->buf;
cnt = pb->width;
if ( is_odd )
ptr += cnt;
cnt >>= 1;
do
{
left = *ptr++;
right = *ptr++;
u8g_dev_ssd1325_2bit_write_4_pixel(u8g, dev, left, right);
cnt--;
} while( cnt > 0 );
}
static uint8_t u8g_dev_ssd1325_nhd27oled_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_dev_ssd1325_2bit_prepare_page(u8g, dev);
u8g_dev_ssd1325_2bit_write_buffer(u8g, dev);
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
}
return u8g_dev_pb8v2_base_fn(u8g, dev, msg, arg);
}
static uint8_t u8g_dev_ssd1325_nhd27oled_2x_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_dev_ssd1325_2bit_2x_prepare_page(u8g, dev, 0);
u8g_dev_ssd1325_2bit_2x_write_buffer(u8g, dev, 0);
u8g_dev_ssd1325_2bit_2x_prepare_page(u8g, dev, 1);
u8g_dev_ssd1325_2bit_2x_write_buffer(u8g, dev, 1);
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
}
return u8g_dev_pb16v2_base_fn(u8g, dev, msg, arg);
}
//U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_sw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_SW_SPI);
//U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_hw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_HW_SPI);
//uint8_t u8g_dev_ssd1325_nhd27oled_2x_buf[WIDTH*2] U8G_NOCOMMON ;
//u8g_pb_t u8g_dev_ssd1325_nhd27oled_2x_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1325_nhd27oled_2x_buf};
//u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_gr_sw_spi = { u8g_dev_ssd1325_nhd27oled_2x_gr_fn, &u8g_dev_ssd1325_nhd27oled_2x_pb, U8G_COM_SW_SPI };
//u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_gr_hw_spi = { u8g_dev_ssd1325_nhd27oled_2x_gr_fn, &u8g_dev_ssd1325_nhd27oled_2x_pb, U8G_COM_HW_SPI };
#endif /* OBSOLETE_CODE */
/*
u8g_dev_ssd1325_nhd27oled_gr.c
2-Bit (gray level) Driver for SSD1325 Controller (OLED Display)
Rewritten with new architecture
Tested with NHD-2.7-12864UCY3
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
SSD130x Monochrom OLED Controller
SSD131x Character OLED Controller
SSD132x Graylevel OLED Controller
SSD1331 Color OLED Controller
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 64
/* http://www.newhavendisplay.com/app_notes/OLED_2_7_12864.txt */
static const uint8_t u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq[] PROGMEM = {
U8G_ESC_DLY(10), /* delay 10 ms */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
0x0ae, /* display off, sleep mode */
0x0b3, 0x091, /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
0x0a8, 0x03f, /* multiplex ratio: 0x03f * 1/64 duty */
0x0a2, 0x04c, /* display offset, shift mapping ram counter */
0x0a1, 0x000, /* display start line */
0x0ad, 0x002, /* master configuration: disable embedded DC-DC, enable internal VCOMH */
0x0a0, 0x052, /* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1), old values: 0x0a0 0x0a6 */
0x086, /* full current range (0x084, 0x085, 0x086) */
0x0b8, /* set gray scale table */
//0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x065, 0x076,
0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x077, 0x077, // 4L mode uses 0, 2, 4, 7
0x081, 0x070, /* contrast, brightness, 0..128, Newhaven: 0x040 */
0x0b2, 0x051, /* frame frequency (row period) */
0x0b1, 0x055, /* phase length */
0x0bc, 0x010, /* pre-charge voltage level */
0x0b4, 0x002, /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0b0, 0x028, /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0be, 0x01c, /* VCOMH voltage */
0x0bf, 0x002|0x00d, /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0a4, /* normal display mode */
0x0af, /* display on */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x015, /* column address... */
0x000, /* start at column 0 */
0x03f, /* end at column 63 (which is y == 127), because there are two pixel in one column */
0x075, /* row address... */
U8G_ESC_END /* end of sequence */
};
static void u8g_dev_ssd1325_gr_prepare_row(u8g_t *u8g, u8g_dev_t *dev, uint8_t delta_row)
{
uint8_t row = ((u8g_pb_t *)(dev->dev_mem))->p.page;
row *= ((u8g_pb_t *)(dev->dev_mem))->p.page_height;
row += delta_row;
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq);
u8g_WriteByte(u8g, dev, row); /* start at the selected row */
u8g_WriteByte(u8g, dev, row+1); /* end within the selected row */
//u8g_SetAddress(u8g, dev, 0); /* instruction mode mode */
//u8g_WriteByte(u8g, dev, 0x05c); /* write to ram */
u8g_SetAddress(u8g, dev, 1); /* data mode */
}
static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0ae, /* display off */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0af, /* display on */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
static uint8_t u8g_dev_ssd1325_nhd27oled_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t i;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
uint8_t *p = pb->buf;
u8g_uint_t cnt;
cnt = pb->width;
cnt >>= 2;
for( i = 0; i < pb->p.page_height; i++ )
{
u8g_dev_ssd1325_gr_prepare_row(u8g, dev, i); /* this will also enable chip select */
u8g_WriteSequence4LTo16GrDevice(u8g, dev, cnt, p);
u8g_SetChipSelect(u8g, dev, 0);
p+=cnt;
}
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
return 1;
}
return u8g_dev_pb8h2_base_fn(u8g, dev, msg, arg);
}
static uint8_t u8g_dev_ssd1325_nhd27oled_2x_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t i;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
uint8_t *p = pb->buf;
u8g_uint_t cnt;
cnt = pb->width;
cnt >>= 2;
for( i = 0; i < pb->p.page_height; i++ )
{
u8g_dev_ssd1325_gr_prepare_row(u8g, dev, i); /* this will also enable chip select */
u8g_WriteSequence4LTo16GrDevice(u8g, dev, cnt, p);
u8g_SetChipSelect(u8g, dev, 0);
p+=cnt;
}
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
return 1;
}
return u8g_dev_pb16h2_base_fn(u8g, dev, msg, arg);
}
U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_sw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_SW_SPI);
U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_hw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_HW_SPI);
uint8_t u8g_dev_ssd1325_nhd27oled_2x_buf[WIDTH*2] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_ssd1325_nhd27oled_2x_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1325_nhd27oled_2x_buf};
u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_gr_sw_spi = { u8g_dev_ssd1325_nhd27oled_2x_gr_fn, &u8g_dev_ssd1325_nhd27oled_2x_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_gr_hw_spi = { u8g_dev_ssd1325_nhd27oled_2x_gr_fn, &u8g_dev_ssd1325_nhd27oled_2x_pb, U8G_COM_HW_SPI };
/*
u8g_dev_ssd1327_96x96_gr.c
2-Bit (graylevel) Driver for SSD1327 Controller (OLED Display)
Tested with Seedstudio 96x96 Oled (LY120)
http://www.seeedstudio.com/wiki/index.php?title=Twig_-_OLED_96x96
Universal 8bit Graphics Library
Copyright (c) 2012, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
SSD130x Monochrom OLED Controller
SSD131x Character OLED Controller
SSD132x Graylevel OLED Controller
SSD1331 Color OLED Controller
*/
#include "u8g.h"
#define WIDTH 96
#define HEIGHT 96
#define XOFFSET 8
/*
http://www.seeedstudio.com/wiki/index.php?title=Twig_-_OLED_96x96
*/
static const uint8_t u8g_dev_ssd1327_2bit_96x96_init_seq[] PROGMEM = {
U8G_ESC_DLY(10), /* delay 10 ms */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
0x0fd, 0x012, /* unlock display, usually not required because the display is unlocked after reset */
0x0ae, /* display off, sleep mode */
0x0a8, 0x05f, /* multiplex ratio: 0x05f * 1/64 duty */
0x0a1, 0x000, /* display start line */
0x0a2, 0x060, /* display offset, shift mapping ram counter */
//0x0a2, 0x04c, /* NHD: display offset, shift mapping ram counter */
0x0a0, 0x046, /* remap configuration, vertical address increment, enable nibble remap (upper nibble is left) */
//0x0a0, 0x056, /* NHD: remap configuration, vertical address increment, enable nibble remap (upper nibble is left) */
0x0ab, 0x001, /* Enable internal VDD regulator (RESET) */
0x081, 0x053, /* contrast, brightness, 0..128, Newhaven: 0x040, LY120 0x053, 0x070 seems also ok */
0x0b1, 0x051, /* phase length */
0x0b3, 0x001, /* set display clock divide ratio/oscillator frequency */
0x0b9, /* use linear lookup table */
#if 0
0x0b8, /* set gray scale table */
//0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x065, 0x076,
0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x077, 0x077, // 4L mode uses 0, 2, 4, 7
#endif
0x0bc, 0x008, /* pre-charge voltage level */
0x0be, 0x007, /* VCOMH voltage */
0x0b6, 0x001, /* second precharge */
0x0d5, 0x062, /* enable second precharge, internal vsl (bit0 = 0) */
#if 0
// the following commands are not used by the SeeedGrayOLED sequence */
0x0ad, 0x002, /* master configuration: disable embedded DC-DC, enable internal VCOMH */
0x086, /* full current range (0x084, 0x085, 0x086) */
0x0b2, 0x051, /* frame frequency (row period) */
0x0b4, 0x002, /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0b0, 0x028, /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
0x0bf, 0x002|0x00d, /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
#endif
0x0a5, /* all pixel on */
//0x02e, /* no scroll (according to SeeedGrayOLED sequence) */
0x0af, /* display on */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a4, /* normal display mode */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a5, /* all pixel on */
0x0af, /* display on */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a4, /* normal display mode */
0x015, /* column address... */
0x008, /* start at column 8, special for the LY120 ??? */
0x037, /* end at column 55, note: there are two pixel in one column */
0x075, /* row address... */
0x008,
0x05f,
U8G_ESC_ADR(1), /* data mode */
0x000f, 0x000f, 0x0000, 0x0000, 0x000f,0x000f,0x0000,0x0000,
0x000f, 0x000f, 0x0000, 0x0000, 0x000f,0x000f,0x0000,0x0000,
0x000f, 0x000f, 0x0000, 0x0000, 0x000f,0x000f,0x0000,0x0000,
0x000f, 0x000f, 0x0000, 0x0000, 0x000f,0x000f,0x0000,0x0000,
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_ssd1327_2bit_96x96_prepare_page_seq[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x015, /* column address... */
XOFFSET, /* start at column 8, special for the LY120 ??? */
0x037, /* end at column 55, note: there are two pixel in one column */
0x075, /* row address... */
U8G_ESC_END /* end of sequence */
};
static void u8g_dev_ssd1327_2bit_prepare_page(u8g_t *u8g, u8g_dev_t *dev)
{
uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1327_2bit_96x96_prepare_page_seq);
page <<= 2;
u8g_WriteByte(u8g, dev, page); /* start at the selected page */
page += 3;
u8g_WriteByte(u8g, dev, page); /* end within the selected page */
u8g_SetAddress(u8g, dev, 1); /* data mode */
}
static void u8g_dev_ssd1327_2bit_2x_prepare_page(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
{
uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1327_2bit_96x96_prepare_page_seq);
page <<= 1;
page += is_odd;
page <<= 2;
u8g_WriteByte(u8g, dev, page); /* start at the selected page */
page += 3;
u8g_WriteByte(u8g, dev, page); /* end within the selected page */
u8g_SetAddress(u8g, dev, 1); /* data mode */
}
/* assumes row autoincrement and activated nibble remap */
static void u8g_dev_ssd1327_2bit_write_4_pixel(u8g_t *u8g, u8g_dev_t *dev, uint8_t left, uint8_t right)
{
uint8_t d, tmp, cnt;
static uint8_t buf[4];
buf[0] = 0;
buf[1] = 0;
buf[2] = 0;
buf[3] = 0;
cnt = 0;
do
{
if ( left == 0 && right == 0 )
break;
d = left;
d &= 3;
d <<= 4;
tmp = right;
tmp &= 3;
d |= tmp;
d <<= 2;
buf[cnt] = d;
left >>= 2;
right >>= 2;
cnt++;
}while ( cnt < 4 );
u8g_WriteSequence(u8g, dev, 4, buf);
}
static void u8g_dev_ssd1327_2bit_write_buffer(u8g_t *u8g, u8g_dev_t *dev)
{
uint8_t cnt, left, right;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
cnt = pb->width;
cnt >>= 1;
ptr = pb->buf;
do
{
left = *ptr++;
right = *ptr++;
u8g_dev_ssd1327_2bit_write_4_pixel(u8g, dev, left, right);
cnt--;
} while( cnt > 0 );
}
static void u8g_dev_ssd1327_2bit_2x_write_buffer(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
{
uint8_t cnt, left, right;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
ptr = pb->buf;
cnt = pb->width;
if ( is_odd )
ptr += cnt;
cnt >>= 1;
do
{
left = *ptr++;
right = *ptr++;
u8g_dev_ssd1327_2bit_write_4_pixel(u8g, dev, left, right);
cnt--;
} while( cnt > 0 );
}
uint8_t u8g_dev_ssd1327_96x96_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1327_2bit_96x96_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_dev_ssd1327_2bit_prepare_page(u8g, dev);
u8g_dev_ssd1327_2bit_write_buffer(u8g, dev);
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
}
return u8g_dev_pb8v2_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_ssd1327_96x96_2x_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1327_2bit_96x96_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_dev_ssd1327_2bit_2x_prepare_page(u8g, dev, 0);
u8g_dev_ssd1327_2bit_2x_write_buffer(u8g, dev, 0);
u8g_dev_ssd1327_2bit_2x_prepare_page(u8g, dev, 1);
u8g_dev_ssd1327_2bit_2x_write_buffer(u8g, dev, 1);
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
}
return u8g_dev_pb16v2_base_fn(u8g, dev, msg, arg);
}
U8G_PB_DEV(u8g_dev_ssd1327_96x96_gr_sw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1327_96x96_gr_fn, U8G_COM_SW_SPI);
U8G_PB_DEV(u8g_dev_ssd1327_96x96_gr_hw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1327_96x96_gr_fn, U8G_COM_HW_SPI);
U8G_PB_DEV(u8g_dev_ssd1327_96x96_gr_i2c , WIDTH, HEIGHT, 4, u8g_dev_ssd1327_96x96_gr_fn, U8G_COM_SSD_I2C);
#define DWIDTH (2*WIDTH)
uint8_t u8g_dev_ssd1327_96x96_2x_buf[DWIDTH] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_ssd1327_96x96_2x_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1327_96x96_2x_buf};
u8g_dev_t u8g_dev_ssd1327_96x96_2x_gr_sw_spi = { u8g_dev_ssd1327_96x96_2x_gr_fn, &u8g_dev_ssd1327_96x96_2x_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_ssd1327_96x96_2x_gr_hw_spi = { u8g_dev_ssd1327_96x96_2x_gr_fn, &u8g_dev_ssd1327_96x96_2x_pb, U8G_COM_HW_SPI };
u8g_dev_t u8g_dev_ssd1327_96x96_2x_gr_i2c = { u8g_dev_ssd1327_96x96_2x_gr_fn, &u8g_dev_ssd1327_96x96_2x_pb, U8G_COM_SSD_I2C };
/*
u8g_dev_ssd1351_128x128.c
Universal 8bit Graphics Library
Copyright (c) 2013, jamjardavies@gmail.com
Copyright (c) 2013, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
History:
Initial version 20 May 2013 jamjardavies@gmail.com
indexed device 22 May 2013 olikraus@gmail.com
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 128
#define PAGE_HEIGHT 8
static const uint8_t u8g_dev_ssd1351_128x128_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_DLY(50),
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_DLY(50),
0xfd, /* Command Lock */
U8G_ESC_ADR(1),
0x12,
U8G_ESC_ADR(0), /* instruction mode */
0xfd,
U8G_ESC_ADR(1),
0xb1, /* Command Lock */
U8G_ESC_ADR(0), /* instruction mode */
0xae, /* Set Display Off */
U8G_ESC_ADR(0), /* instruction mode */
0xb3,
U8G_ESC_ADR(1),
0xf1, /* Front Clock Div */
U8G_ESC_ADR(0), /* instruction mode */
0xca,
U8G_ESC_ADR(1),
0x7f, /* Set Multiplex Ratio */
U8G_ESC_ADR(0), /* instruction mode */
0xa0,
U8G_ESC_ADR(1),
0xb4, /* Set Colour Depth */
U8G_ESC_ADR(0), /* instruction mode */
0x15,
U8G_ESC_ADR(1),
0x00, 0x7f, /* Set Column Address */
U8G_ESC_ADR(0), /* instruction mode */
0x75,
U8G_ESC_ADR(1),
0x00, 0x7f, /* Set Row Address */
U8G_ESC_ADR(0), /* instruction mode */
0xa1,
U8G_ESC_ADR(1),
0x00, /* Set Display Start Line */
U8G_ESC_ADR(0), /* instruction mode */
0xa2,
U8G_ESC_ADR(1),
0x00, /* Set Display Offset */
U8G_ESC_ADR(0), /* instruction mode */
0xb5,
U8G_ESC_ADR(1),
0x00, /* Set GPIO */
U8G_ESC_ADR(0), /* instruction mode */
0xab,
U8G_ESC_ADR(1),
0x01, /* Set Function Selection */
U8G_ESC_ADR(0), /* instruction mode */
0xb1,
U8G_ESC_ADR(1),
0x32, /* Set Phase Length */
U8G_ESC_ADR(0), /* instruction mode */
0xb4,
U8G_ESC_ADR(1),
0xa0, 0xb5, 0x55, /* Set Segment Low Voltage */
U8G_ESC_ADR(0), /* instruction mode */
0xbb,
U8G_ESC_ADR(1),
0x17, /* Set Precharge Voltage */
U8G_ESC_ADR(0), /* instruction mode */
0xbe,
U8G_ESC_ADR(1),
0x05, /* Set VComH Voltage */
U8G_ESC_ADR(0), /* instruction mode */
0xc1,
U8G_ESC_ADR(1),
0xc8, 0x80, 0xc8, /* Set Contrast */
U8G_ESC_ADR(0), /* instruction mode */
0xc7,
U8G_ESC_ADR(1),
0x0f, /* Set Master Contrast */
U8G_ESC_ADR(0), /* instruction mode */
0xb6,
U8G_ESC_ADR(1),
0x01, /* Set Second Precharge Period */
U8G_ESC_ADR(0), /* instruction mode */
0xa6, /* Set Display Mode Reset */
U8G_ESC_ADR(0), /* instruction mode */
0xb8, /* Set CMD Grayscale Lookup */
U8G_ESC_ADR(1),
0x05,
0x06,
0x07,
0x08,
0x09,
0x0a,
0x0b,
0x0c,
0x0D,
0x0E,
0x0F,
0x10,
0x11,
0x12,
0x13,
0x14,
0x15,
0x16,
0x18,
0x1a,
0x1b,
0x1C,
0x1D,
0x1F,
0x21,
0x23,
0x25,
0x27,
0x2A,
0x2D,
0x30,
0x33,
0x36,
0x39,
0x3C,
0x3F,
0x42,
0x45,
0x48,
0x4C,
0x50,
0x54,
0x58,
0x5C,
0x60,
0x64,
0x68,
0x6C,
0x70,
0x74,
0x78,
0x7D,
0x82,
0x87,
0x8C,
0x91,
0x96,
0x9B,
0xA0,
0xA5,
0xAA,
0xAF,
0xB4,
U8G_ESC_ADR(0),
0xaf, /* Set Display On */
0x5c,
U8G_ESC_DLY(50),
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(1),
U8G_ESC_END /* end of sequence */
};
/* set gpio to high */
static const uint8_t u8g_dev_ssd1351_128x128gh_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_DLY(50),
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_DLY(50),
0xfd, /* Command Lock */
U8G_ESC_ADR(1),
0x12,
U8G_ESC_ADR(0), /* instruction mode */
0xfd,
U8G_ESC_ADR(1),
0xb1, /* Command Lock */
U8G_ESC_ADR(0), /* instruction mode */
0xae, /* Set Display Off */
U8G_ESC_ADR(0), /* instruction mode */
0xb3,
U8G_ESC_ADR(1),
0xf1, /* Front Clock Div */
U8G_ESC_ADR(0), /* instruction mode */
0xca,
U8G_ESC_ADR(1),
0x7f, /* Set Multiplex Ratio */
U8G_ESC_ADR(0), /* instruction mode */
0xa0,
U8G_ESC_ADR(1),
0xb4, /* Set Colour Depth */
U8G_ESC_ADR(0), /* instruction mode */
0x15,
U8G_ESC_ADR(1),
0x00, 0x7f, /* Set Column Address */
U8G_ESC_ADR(0), /* instruction mode */
0x75,
U8G_ESC_ADR(1),
0x00, 0x7f, /* Set Row Address */
U8G_ESC_ADR(0), /* instruction mode */
0xa1,
U8G_ESC_ADR(1),
0x00, /* Set Display Start Line */
U8G_ESC_ADR(0), /* instruction mode */
0xa2,
U8G_ESC_ADR(1),
0x00, /* Set Display Offset */
U8G_ESC_ADR(0), /* instruction mode */
0xb5,
U8G_ESC_ADR(1),
0x03, /* Set GPIO to High Level */
U8G_ESC_ADR(0), /* instruction mode */
0xab,
U8G_ESC_ADR(1),
0x01, /* Set Function Selection */
U8G_ESC_ADR(0), /* instruction mode */
0xb1,
U8G_ESC_ADR(1),
0x32, /* Set Phase Length */
U8G_ESC_ADR(0), /* instruction mode */
0xb4,
U8G_ESC_ADR(1),
0xa0, 0xb5, 0x55, /* Set Segment Low Voltage */
U8G_ESC_ADR(0), /* instruction mode */
0xbb,
U8G_ESC_ADR(1),
0x17, /* Set Precharge Voltage */
U8G_ESC_ADR(0), /* instruction mode */
0xbe,
U8G_ESC_ADR(1),
0x05, /* Set VComH Voltage */
U8G_ESC_ADR(0), /* instruction mode */
0xc1,
U8G_ESC_ADR(1),
0xc8, 0x80, 0xc8, /* Set Contrast */
U8G_ESC_ADR(0), /* instruction mode */
0xc7,
U8G_ESC_ADR(1),
0x0f, /* Set Master Contrast */
U8G_ESC_ADR(0), /* instruction mode */
0xb6,
U8G_ESC_ADR(1),
0x01, /* Set Second Precharge Period */
U8G_ESC_ADR(0), /* instruction mode */
0xa6, /* Set Display Mode Reset */
U8G_ESC_ADR(0), /* instruction mode */
0xb8, /* Set CMD Grayscale Lookup */
U8G_ESC_ADR(1),
0x05,
0x06,
0x07,
0x08,
0x09,
0x0a,
0x0b,
0x0c,
0x0D,
0x0E,
0x0F,
0x10,
0x11,
0x12,
0x13,
0x14,
0x15,
0x16,
0x18,
0x1a,
0x1b,
0x1C,
0x1D,
0x1F,
0x21,
0x23,
0x25,
0x27,
0x2A,
0x2D,
0x30,
0x33,
0x36,
0x39,
0x3C,
0x3F,
0x42,
0x45,
0x48,
0x4C,
0x50,
0x54,
0x58,
0x5C,
0x60,
0x64,
0x68,
0x6C,
0x70,
0x74,
0x78,
0x7D,
0x82,
0x87,
0x8C,
0x91,
0x96,
0x9B,
0xA0,
0xA5,
0xAA,
0xAF,
0xB4,
U8G_ESC_ADR(0),
0xaf, /* Set Display On */
0x5c,
U8G_ESC_DLY(50),
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(1),
U8G_ESC_END /* end of sequence */
};
#define u8g_dev_ssd1351_128x128_init_seq u8g_dev_ssd1351_128x128_init_seq
static const uint8_t u8g_dev_ssd1351_128x128_column_seq[] PROGMEM = {
U8G_ESC_CS(1),
U8G_ESC_ADR(0), 0x15,
U8G_ESC_ADR(1), 0x00, 0x7f,
U8G_ESC_ADR(0), 0x75,
U8G_ESC_ADR(1), 0x00, 0x7f,
U8G_ESC_ADR(0), 0x5c,
U8G_ESC_ADR(1),
U8G_ESC_CS(0),
U8G_ESC_END
};
#define RGB332_STREAM_BYTES 8
static uint8_t u8g_ssd1351_stream_bytes[RGB332_STREAM_BYTES*3];
void u8g_ssd1351_to_stream(uint8_t *ptr)
{
uint8_t cnt = RGB332_STREAM_BYTES;
uint8_t val;
uint8_t *dest = u8g_ssd1351_stream_bytes;
for( cnt = 0; cnt < RGB332_STREAM_BYTES; cnt++ )
{
val = *ptr++;
*dest++ = ((val & 0xe0) >> 2);
*dest++ = ((val & 0x1c) << 1);
*dest++ = ((val & 0x03) << 4);
}
}
#ifdef OBSOLETE
// Convert the internal RGB 332 to R
static uint8_t u8g_ssd1351_get_r(uint8_t colour)
{
//return ((colour & 0xe0) >> 5) * 9;
//return ((colour & 0xe0) >> 5) * 8;
return ((colour & 0xe0) >> 2) ;
}
// Convert the internal RGB 332 to G
static uint8_t u8g_ssd1351_get_g(uint8_t colour)
{
//return ((colour & 0x1c) >> 2) * 9;
//return ((colour & 0x1c) >> 2) * 8;
return ((colour & 0x1c) << 1);
}
// Convert the internal RGB 332 to B
static uint8_t u8g_ssd1351_get_b(uint8_t colour)
{
//return (colour & 0x03) * 21;
return (colour & 0x03) * 16;
}
#endif
uint8_t u8g_dev_ssd1351_128x128_332_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
// u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_FIRST:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_uint_t x;
uint8_t page_height;
uint8_t i;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
uint8_t *ptr = pb->buf;
u8g_SetChipSelect(u8g, dev, 1);
page_height = pb->p.page_y1;
page_height -= pb->p.page_y0;
page_height++;
for( i = 0; i < page_height; i++ )
{
for (x = 0; x < pb->width; x+=RGB332_STREAM_BYTES)
{
u8g_ssd1351_to_stream(ptr);
u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
ptr += RGB332_STREAM_BYTES;
}
}
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_GET_MODE:
return U8G_MODE_R3G3B2;
}
return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_ssd1351_128x128gh_332_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
// u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128gh_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_FIRST:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_uint_t x;
uint8_t page_height;
uint8_t i;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
uint8_t *ptr = pb->buf;
u8g_SetChipSelect(u8g, dev, 1);
page_height = pb->p.page_y1;
page_height -= pb->p.page_y0;
page_height++;
for( i = 0; i < page_height; i++ )
{
for (x = 0; x < pb->width; x+=RGB332_STREAM_BYTES)
{
u8g_ssd1351_to_stream(ptr);
u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
ptr += RGB332_STREAM_BYTES;
}
}
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_GET_MODE:
return U8G_MODE_R3G3B2;
}
return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
}
static uint8_t u8g_dev_ssd1351_128x128_r[256];
static uint8_t u8g_dev_ssd1351_128x128_g[256];
static uint8_t u8g_dev_ssd1351_128x128_b[256];
uint8_t u8g_dev_ssd1351_128x128_idx_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
// u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_SET_COLOR_ENTRY:
u8g_dev_ssd1351_128x128_r[ ((u8g_dev_arg_irgb_t *)arg)->idx ] = ((u8g_dev_arg_irgb_t *)arg)->r;
u8g_dev_ssd1351_128x128_g[ ((u8g_dev_arg_irgb_t *)arg)->idx ] = ((u8g_dev_arg_irgb_t *)arg)->g;
u8g_dev_ssd1351_128x128_b[ ((u8g_dev_arg_irgb_t *)arg)->idx ] = ((u8g_dev_arg_irgb_t *)arg)->b;
break;
case U8G_DEV_MSG_PAGE_FIRST:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
int x;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
uint8_t *ptr = pb->buf;
u8g_SetChipSelect(u8g, dev, 1);
for (x = 0; x < pb->width; x++)
{
u8g_WriteByte(u8g, dev, u8g_dev_ssd1351_128x128_r[(*ptr)>>2]);
u8g_WriteByte(u8g, dev, u8g_dev_ssd1351_128x128_g[(*ptr)>>2]);
u8g_WriteByte(u8g, dev, u8g_dev_ssd1351_128x128_b[(*ptr)>>2]);
ptr++;
}
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_GET_MODE:
return U8G_MODE_INDEX;
}
return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
}
void u8g_ssd1351_hicolor_to_stream(uint8_t *ptr)
{
register uint8_t cnt = RGB332_STREAM_BYTES;
register uint8_t low, high, r, g, b;
uint8_t *dest = u8g_ssd1351_stream_bytes;
for( cnt = 0; cnt < RGB332_STREAM_BYTES; cnt++ )
{
low = *ptr++;
high = *ptr++;
r = high & ~7;
r >>= 2;
b = low & 31;
b <<= 1;
g = high & 7;
g <<= 3;
g |= (low>>5)&7;
*dest++ = r;
*dest++ = g;
*dest++ = b;
}
}
uint8_t u8g_dev_ssd1351_128x128_hicolor_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_FIRST:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
uint8_t i, j;
uint8_t page_height;
uint8_t *ptr = pb->buf;
u8g_SetChipSelect(u8g, dev, 1);
page_height = pb->p.page_y1;
page_height -= pb->p.page_y0;
page_height++;
for( j = 0; j < page_height; j++ )
{
for (i = 0; i < pb->width; i+=RGB332_STREAM_BYTES)
{
u8g_ssd1351_hicolor_to_stream(ptr);
u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
ptr += RGB332_STREAM_BYTES*2;
}
}
u8g_SetChipSelect(u8g, dev, 0);
}
break; /* continue to base fn */
case U8G_DEV_MSG_GET_MODE:
return U8G_MODE_HICOLOR;
}
return u8g_dev_pbxh16_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_ssd1351_128x128gh_hicolor_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128gh_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_FIRST:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
uint8_t i, j;
uint8_t page_height;
uint8_t *ptr = pb->buf;
u8g_SetChipSelect(u8g, dev, 1);
page_height = pb->p.page_y1;
page_height -= pb->p.page_y0;
page_height++;
for( j = 0; j < page_height; j++ )
{
for (i = 0; i < pb->width; i+=RGB332_STREAM_BYTES)
{
u8g_ssd1351_hicolor_to_stream(ptr);
u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
ptr += RGB332_STREAM_BYTES*2;
}
}
u8g_SetChipSelect(u8g, dev, 0);
}
break; /* continue to base fn */
case U8G_DEV_MSG_GET_MODE:
return U8G_MODE_HICOLOR;
}
return u8g_dev_pbxh16_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_ssd1351_128x128_byte_buf[WIDTH*PAGE_HEIGHT] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_ssd1351_128x128_byte_pb = { {PAGE_HEIGHT, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1351_128x128_byte_buf};
u8g_dev_t u8g_dev_ssd1351_128x128_332_sw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_ssd1351_128x128_332_hw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_HW_SPI };
u8g_dev_t u8g_dev_ssd1351_128x128gh_332_sw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_ssd1351_128x128gh_332_hw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_HW_SPI };
//u8g_dev_t u8g_dev_ssd1351_128x128_idx_sw_spi = { u8g_dev_ssd1351_128x128_idx_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_SW_SPI };
//u8g_dev_t u8g_dev_ssd1351_128x128_idx_hw_spi = { u8g_dev_ssd1351_128x128_idx_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_HW_SPI };
/* only half of the height, because two bytes are needed for one pixel */
u8g_pb_t u8g_dev_ssd1351_128x128_hicolor_byte_pb = { {PAGE_HEIGHT/2, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1351_128x128_byte_buf};
u8g_dev_t u8g_dev_ssd1351_128x128_hicolor_sw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_ssd1351_128x128_hicolor_hw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_HW_SPI };
u8g_dev_t u8g_dev_ssd1351_128x128gh_hicolor_sw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_ssd1351_128x128gh_hicolor_hw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_HW_SPI };
uint8_t u8g_dev_ssd1351_128x128_4x_byte_buf[WIDTH*PAGE_HEIGHT*4] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_ssd1351_128x128_4x_332_byte_pb = { {PAGE_HEIGHT*4, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1351_128x128_4x_byte_buf};
u8g_dev_t u8g_dev_ssd1351_128x128_4x_332_sw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_ssd1351_128x128_4x_332_hw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_HW_SPI };
u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_332_sw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_332_hw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_HW_SPI };
u8g_pb_t u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb = { {PAGE_HEIGHT/2*4, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1351_128x128_4x_byte_buf};
u8g_dev_t u8g_dev_ssd1351_128x128_4x_hicolor_sw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_ssd1351_128x128_4x_hicolor_hw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_HW_SPI };
u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_hicolor_sw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_hicolor_hw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_HW_SPI };
/*
U8G_PB_DEV(u8g_dev_ssd1351_128x128_332_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_332_fn, U8G_COM_SW_SPI);
U8G_PB_DEV(u8g_dev_ssd1351_128x128_332_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_332_fn, U8G_COM_HW_SPI);
U8G_PB_DEV(u8g_dev_ssd1351_128x128_idx_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_idx_fn, U8G_COM_SW_SPI);
U8G_PB_DEV(u8g_dev_ssd1351_128x128_idx_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_idx_fn, U8G_COM_HW_SPI);
*/
/*
u8g_dev_st7565_64128n.c (Displaytech)
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 64
#define PAGE_HEIGHT 8
/* init sequence from https://github.com/adafruit/ST7565-LCD/blob/master/ST7565/ST7565.cpp */
static const uint8_t u8g_dev_st7565_64128n_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
0x0A2, /* 0x0a2: LCD bias 1/9 (according to Displaytech 64128N datasheet) */
0x0A0, /* Normal ADC Select (according to Displaytech 64128N datasheet) */
0x0c8, /* common output mode: set scan direction normal operation/SHL Select, 0x0c0 --> SHL = 0, normal, 0x0c8 --> SHL = 1 */
0x040, /* Display start line for Displaytech 64128N */
0x028 | 0x04, /* power control: turn on voltage converter */
U8G_ESC_DLY(50), /* delay 50 ms */
0x028 | 0x06, /* power control: turn on voltage regulator */
U8G_ESC_DLY(50), /* delay 50 ms */
0x028 | 0x07, /* power control: turn on voltage follower */
U8G_ESC_DLY(50), /* delay 50 ms */
0x010, /* Set V0 voltage resistor ratio. Setting for controlling brightness of Displaytech 64128N */
0x0a6, /* display normal, bit val 0: LCD pixel off. */
0x081, /* set contrast */
0x01e, /* Contrast value. Setting for controlling brightness of Displaytech 64128N */
0x0af, /* display on */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a5, /* display all points, ST7565 */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a4, /* normal display */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_64128n_data_start[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x010, /* set upper 4 bit of the col adr to 0x10 */
0x000, /* set lower 4 bit of the col adr to 0x00. Changed for DisplayTech 64128N */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_64128n_sleep_on[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0ac, /* static indicator off */
0x000, /* indicator register set (not sure if this is required) */
0x0ae, /* display off */
0x0a5, /* all points on */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_64128n_sleep_off[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0a4, /* all points off */
0x0af, /* display on */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
uint8_t u8g_dev_st7565_64128n_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
return 0;
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_sleep_off);
return 1;
}
return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_st7565_64128n_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page)); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, pb->width, pb->buf);
u8g_SetChipSelect(u8g, dev, 0);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_sleep_off);
return 1;
}
return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
}
U8G_PB_DEV(u8g_dev_st7565_64128n_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_64128n_fn, U8G_COM_SW_SPI);
U8G_PB_DEV(u8g_dev_st7565_64128n_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_64128n_fn, U8G_COM_HW_SPI);
U8G_PB_DEV(u8g_dev_st7565_64128n_parallel, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_64128n_fn, U8G_COM_PARALLEL);
uint8_t u8g_dev_st7565_64128n_2x_buf[WIDTH*2] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_st7565_64128n_2x_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_st7565_64128n_2x_buf};
u8g_dev_t u8g_dev_st7565_64128n_2x_sw_spi = { u8g_dev_st7565_64128n_2x_fn, &u8g_dev_st7565_64128n_2x_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_st7565_64128n_2x_hw_spi = { u8g_dev_st7565_64128n_2x_fn, &u8g_dev_st7565_64128n_2x_pb, U8G_COM_HW_SPI };
u8g_dev_t u8g_dev_st7565_64128n_2x_hw_parallel = { u8g_dev_st7565_64128n_2x_fn, &u8g_dev_st7565_64128n_2x_pb, U8G_COM_PARALLEL };
/*
u8g_dev_st7565_dogm128.c
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 64
#define PAGE_HEIGHT 8
const uint8_t u8g_dev_st7565_dogm128_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
0x040, /* set display start line */
0x0a1, /* ADC set to reverse */
0x0c0, /* common output mode: set scan direction normal operation */
0x0a6, /* display normal (none reverse) */
0x0a2, /* LCD bias 1/9 */
0x02f, /* all power control circuits on */
0x0f8, /* set booster ratio to */
0x000, /* 4x */
0x027, /* set V0 voltage resistor ratio to large */
0x081, /* set contrast */
0x018, /* contrast value, EA default: 0x016 */
0x0ac, /* indicator */
0x000, /* disable */
0x0a4, /* normal display (not all on) */
0x0af, /* display on */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_dogm128_data_start[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x010, /* set upper 4 bit of the col adr to 0 */
0x000, /* set lower 4 bit of the col adr to 0 */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_dogm128_sleep_on[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0ac, /* static indicator off */
0x000, /* indicator register set (not sure if this is required) */
0x0ae, /* display off */
0x0a5, /* all points on */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_dogm128_sleep_off[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0a4, /* all points off */
0x0af, /* display on */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
uint8_t u8g_dev_st7565_dogm128_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm128_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm128_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
return 0;
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm128_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm128_sleep_off);
return 1;
}
return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_st7565_dogm128_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm128_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm128_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page)); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, pb->width, pb->buf);
u8g_SetChipSelect(u8g, dev, 0);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm128_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm128_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm128_sleep_off);
return 1;
}
return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
}
U8G_PB_DEV(u8g_dev_st7565_dogm128_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_dogm128_fn, U8G_COM_SW_SPI);
U8G_PB_DEV(u8g_dev_st7565_dogm128_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_dogm128_fn, U8G_COM_HW_SPI);
U8G_PB_DEV(u8g_dev_st7565_dogm128_parallel, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_dogm128_fn, U8G_COM_PARALLEL);
uint8_t u8g_dev_st7565_dogm128_2x_buf[WIDTH*2] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_st7565_dogm128_2x_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_st7565_dogm128_2x_buf};
u8g_dev_t u8g_dev_st7565_dogm128_2x_sw_spi = { u8g_dev_st7565_dogm128_2x_fn, &u8g_dev_st7565_dogm128_2x_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_st7565_dogm128_2x_hw_spi = { u8g_dev_st7565_dogm128_2x_fn, &u8g_dev_st7565_dogm128_2x_pb, U8G_COM_HW_SPI };
u8g_dev_t u8g_dev_st7565_dogm128_2x_parallel = { u8g_dev_st7565_dogm128_2x_fn, &u8g_dev_st7565_dogm128_2x_pb, U8G_COM_PARALLEL };
/*
u8g_dev_st7565_dogm132.c
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 132
#define HEIGHT 32
#define PAGE_HEIGHT 8
static const uint8_t u8g_dev_st7565_dogm132_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
0x040, /* set display start line to 0 */
0x0a1, /* ADC set to reverse */
0x0c0, /* common output mode */
0x0a6, /* display normal, bit val 0: LCD pixel off. */
0x0a2, /* LCD bias 1/9 */
0x02f, /* all power control circuits on */
0x0f8, /* set booster ratio to */
0x000, /* 4x */
0x023, /* set V0 voltage resistor ratio to large */
0x081, /* set contrast */
0x01f, /* contrast value, EA default: 0x01f */
0x0ac, /* indicator */
0x000, /* disable */
0x0af, /* display on */
#ifdef OBSOLETE_DOGM128
0x040, /* set display start line */
0x0c8, /* set scan direction inverse operation */
0x0a2, /* LCD bias 1/9 */
0x02f, /* all power control circuits on */
0x0f8, /* set booster ratio to */
0x000, /* 4x */
0x027, /* set V0 voltage resistor ratio to large */
0x081, /* set contrast */
0x018, /* contrast value, EA default: 0x016 */
0x0ac, /* indicator */
0x000, /* disable */
0x0af, /* display on */
#endif
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a5, /* display all points, ST7565 */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a4, /* normal display */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_dogm132_data_start[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x010, /* set upper 4 bit of the col adr to 0 */
0x000, /* set lower 4 bit of the col adr to 0 */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_dogm132_sleep_on[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0ac, /* static indicator off */
0x000, /* indicator register set (not sure if this is required) */
0x0ae, /* display off */
0x0a5, /* all points on */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_dogm132_sleep_off[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0a4, /* all points off */
0x0af, /* display on */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
uint8_t u8g_dev_st7565_dogm132_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm132_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm132_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
return 0;
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm132_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_dogm132_sleep_off);
return 1;
}
return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
}
U8G_PB_DEV(u8g_dev_st7565_dogm132_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_dogm132_fn, U8G_COM_SW_SPI);
U8G_PB_DEV(u8g_dev_st7565_dogm132_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_dogm132_fn, U8G_COM_HW_SPI);
/*
u8g_dev_st7565_lm6059.c (Adafruit display)
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 64
#define PAGE_HEIGHT 8
/* init sequence from https://github.com/adafruit/ST7565-LCD/blob/master/ST7565/ST7565.cpp */
static const uint8_t u8g_dev_st7565_lm6059_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
0x0a3, /* 0x0a2: LCD bias 1/9 (suggested for the LM6063), 0x0a3: Used by Adafruit, 0x0a2 does not work */
/* the LM6059 vs LM6063, ADC and SHL have inverted settings */
0x0a0, /* 0x0a1: ADC set to normal (suggested for the LM6059), 0x0a0: Used by Adafruit -> normal mode */
0x0c8, /* common output mode: set scan direction normal operation/SHL Select, 0x0c0 --> SHL = 0, normal, 0x0c8 --> SHL = 1 */
0x060, /* set display start line */
0x028 | 0x04, /* power control: turn on voltage converter */
U8G_ESC_DLY(50), /* delay 50 ms */
0x028 | 0x06, /* power control: turn on voltage regulator */
U8G_ESC_DLY(50), /* delay 50 ms */
0x028 | 0x07, /* power control: turn on voltage follower */
U8G_ESC_DLY(50), /* delay 50 ms */
0x026, /* set V0 voltage resistor ratio to 6 (Adafruit Value, no info from LM6063 Manual) */
0x0a6, /* display normal, bit val 0: LCD pixel off. */
0x081, /* set contrast */
0x018, /* contrast value*/
/*0x0ac,*/ /* indicator */
/*0x000,*/ /* disable */
0x0af, /* display on */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a5, /* display all points, ST7565 */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a4, /* normal display */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_lm6059_data_start[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x010, /* set upper 4 bit of the col adr to 0 */
0x001, /* set lower 4 bit of the col adr */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_lm6059_sleep_on[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0ac, /* static indicator off */
0x000, /* indicator register set (not sure if this is required) */
0x0ae, /* display off */
0x0a5, /* all points on */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_lm6059_sleep_off[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0a4, /* all points off */
0x0af, /* display on */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
uint8_t u8g_dev_st7565_lm6059_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_lm6059_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_lm6059_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
return 0;
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_lm6059_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_lm6059_sleep_off);
return 1;
}
return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_st7565_lm6059_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_lm6059_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_lm6059_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page)); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, pb->width, pb->buf);
u8g_SetChipSelect(u8g, dev, 0);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_lm6059_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_lm6059_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_lm6059_sleep_off);
return 1;
}
return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
}
U8G_PB_DEV(u8g_dev_st7565_lm6059_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_lm6059_fn, U8G_COM_SW_SPI);
U8G_PB_DEV(u8g_dev_st7565_lm6059_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_lm6059_fn, U8G_COM_HW_SPI);
uint8_t u8g_dev_st7565_lm6059_2x_buf[WIDTH*2] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_st7565_lm6059_2x_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_st7565_lm6059_2x_buf};
u8g_dev_t u8g_dev_st7565_lm6059_2x_sw_spi = { u8g_dev_st7565_lm6059_2x_fn, &u8g_dev_st7565_lm6059_2x_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_st7565_lm6059_2x_hw_spi = { u8g_dev_st7565_lm6059_2x_fn, &u8g_dev_st7565_lm6059_2x_pb, U8G_COM_HW_SPI };
/*
u8g_dev_st7565_lm6063.c
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 64
#define PAGE_HEIGHT 8
#ifdef OLD_ADAFRUIT_CODE
static const uint8_t OLD_u8g_dev_st7565_lm6063_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
0x040, /* set display start line */
0x0a1, /* ADC set to reverse */
0x0c8, /* common output mode: set scan direction normal operation/SHL Select / 17 Jan: seems to be a bug, must be 0x0c0 */
0x0a6, /* display normal, bit val 0: LCD pixel off. */
0x0a2, /* LCD bias 1/9 */
0x02f, /* all power control circuits on */
/*0x0f8,*/ /* set booster ratio to */
/*0x000, */ /* 4x */
/*0x027,*/ /* set V0 voltage resistor ratio to large */
0x081, /* set contrast */
0x018, /* contrast value*/
0x0ac, /* indicator */
0x000, /* disable */
0x0af, /* display on */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a5, /* display all points, ST7565 */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a4, /* normal display */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
#endif
/* init sequence from https://github.com/adafruit/ST7565-LCD/blob/master/ST7565/ST7565.cpp */
static const uint8_t u8g_dev_st7565_lm6063_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
0x0a3, /* 0x0a2: LCD bias 1/9 (suggested for the LM6063), 0x0a3: Used by Adafruit */
0x0a1, /* 0x0a1: ADC set to reverse (suggested for the LM6063), 0x0a0: Used by Adafruit -> normal mode */
0x0c0, /* common output mode: set scan direction normal operation/SHL Select, 0x0c0 --> SHL = 0, normal, 0x0c8 --> SHL = 1 */
0x040, /* set display start line */
0x028 | 0x04, /* power control: turn on voltage converter */
U8G_ESC_DLY(50), /* delay 50 ms */
0x028 | 0x06, /* power control: turn on voltage regulator */
U8G_ESC_DLY(50), /* delay 50 ms */
0x028 | 0x07, /* power control: turn on voltage follower */
U8G_ESC_DLY(50), /* delay 50 ms */
0x026, /* set V0 voltage resistor ratio to 6 (Adafruit Value, no info from LM6063 Manual) */
0x0a6, /* display normal, bit val 0: LCD pixel off. */
0x081, /* set contrast */
0x018, /* contrast value*/
/*0x0ac,*/ /* indicator */
/*0x000,*/ /* disable */
0x0af, /* display on */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a5, /* display all points, ST7565 */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a4, /* normal display */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_lm6063_data_start[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x010, /* set upper 4 bit of the col adr to 0 */
0x000, /* set lower 4 bit of the col adr to 0 */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_st7565_sleep_on[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0ac, /* static indicator off */
0x000, /* indicator register set (not sure if this is required) */
0x0ae, /* display off */
0x0a5, /* all points on */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_st7565_sleep_off[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0a4, /* all points off */
0x0af, /* display on */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
uint8_t u8g_dev_st7565_lm6063_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_lm6063_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_lm6063_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
return 0;
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_st7565_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_st7565_sleep_off);
return 1;
}
return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_st7565_lm6063_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_lm6063_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_lm6063_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page)); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, pb->width, pb->buf);
u8g_SetChipSelect(u8g, dev, 0);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_lm6063_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_st7565_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_st7565_sleep_off);
return 1;
}
return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
}
U8G_PB_DEV(u8g_dev_st7565_lm6063_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_lm6063_fn, U8G_COM_SW_SPI);
U8G_PB_DEV(u8g_dev_st7565_lm6063_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_lm6063_fn, U8G_COM_HW_SPI);
uint8_t u8g_dev_st7565_lm6063_2x_buf[WIDTH*2] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_st7565_lm6063_2x_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_st7565_lm6063_2x_buf};
u8g_dev_t u8g_dev_st7565_lm6063_2x_sw_spi = { u8g_dev_st7565_lm6063_2x_fn, &u8g_dev_st7565_lm6063_2x_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_st7565_lm6063_2x_hw_spi = { u8g_dev_st7565_lm6063_2x_fn, &u8g_dev_st7565_lm6063_2x_pb, U8G_COM_HW_SPI };
/*
u8g_dev_st7565_nhd_c12832.c
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 32
#define PAGE_HEIGHT 8
static const uint8_t u8g_dev_st7565_c12832_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
0x040, /* set display start line to 0 */
0x0a0, /* ADC set, values: a0=normal, a1=reverse */
0x0c8, /* common output mode: c0=normal, c8=reverse */
0x0a6, /* display normal, bit val 0: LCD pixel off. */
0x0a2, /* LCD bias 1/9 */
0x02f, /* all power control circuits on */
0x0f8, /* set booster ratio to */
0x000, /* 4x */
0x023, /* set V0 voltage resistor ratio to large */
0x081, /* set contrast */
0x00a, /* contrast value */
0x0ac, /* indicator */
0x000, /* disable */
0x0af, /* display on */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a5, /* display all points, ST7565 */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a4, /* normal display */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_c12832_data_start[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x010, /* set upper 4 bit of the col adr to 0 */
0x000, /* set lower 4 bit of the col adr to 0 */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_c12832_sleep_on[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0ac, /* static indicator off */
0x000, /* indicator register set (not sure if this is required) */
0x0ae, /* display off */
0x0a5, /* all points on */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_c12832_sleep_off[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0a4, /* all points off */
0x0af, /* display on */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
uint8_t u8g_dev_st7565_c12832_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_c12832_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_c12832_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
return 0;
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_c12832_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_c12832_sleep_off);
return 1;
}
return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
}
U8G_PB_DEV(u8g_dev_st7565_nhd_c12832_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_c12832_fn, U8G_COM_SW_SPI);
U8G_PB_DEV(u8g_dev_st7565_nhd_c12832_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_c12832_fn, U8G_COM_HW_SPI);
U8G_PB_DEV(u8g_dev_st7565_nhd_c12832_parallel, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_c12832_fn, U8G_COM_PARALLEL);
U8G_PB_DEV(u8g_dev_st7565_nhd_c12832_hw_usart_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_c12832_fn, U8G_COM_HW_USART_SPI);
/*
u8g_dev_st7565_nhd_c12864.c
Support for the NHD-C12864A1Z-FSB-FBW (Newhaven Display)
Universal 8bit Graphics Library
Copyright (c) 2012, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 64
#define PAGE_HEIGHT 8
const uint8_t u8g_dev_st7565_nhd_c12864_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(10), /* do reset low pulse with (10*16)+2 milliseconds */
U8G_ESC_CS(1), /* enable chip */
0x040, /* set display start line */
0x0a1, /* ADC set to reverse */
0x0c0, /* common output mode: set scan direction normal operation */
0x0a6, /* display normal, bit val 0: LCD pixel off. */
0x0a2, /* LCD bias 1/9 */
0x02f, /* all power control circuits on */
0x0f8, /* set booster ratio to */
0x000, /* 4x */
0x027, /* set V0 voltage resistor ratio to large */
0x081, /* set contrast */
0x008, /* contrast: 0x008 is a good value for NHD C12864, Nov 2012: User reports that 0x1a is much better */
0x0ac, /* indicator */
0x000, /* disable */
0x0af, /* display on */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a5, /* display all points, ST7565 */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0a4, /* normal display */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_nhd_c12864_data_start[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x010, /* set upper 4 bit of the col adr to 0 */
0x004, /* set lower 4 bit of the col adr to 4 (NHD C12864) */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_c12864_sleep_on[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0ac, /* static indicator off */
0x000, /* indicator register set (not sure if this is required) */
0x0ae, /* display off */
0x0a5, /* all points on */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
static const uint8_t u8g_dev_st7565_c12864_sleep_off[] PROGMEM = {
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
0x0a4, /* all points off */
0x0af, /* display on */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
U8G_ESC_END /* end of sequence */
};
uint8_t u8g_dev_st7565_nhd_c12864_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_nhd_c12864_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_nhd_c12864_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
return 0;
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_c12864_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_c12864_sleep_off);
return 1;
}
return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_st7565_nhd_c12864_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_nhd_c12864_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_nhd_c12864_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page)); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, pb->width, pb->buf);
u8g_SetChipSelect(u8g, dev, 0);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_nhd_c12864_data_start);
u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
u8g_SetChipSelect(u8g, dev, 0);
}
break;
case U8G_DEV_MSG_CONTRAST:
u8g_SetChipSelect(u8g, dev, 1);
u8g_SetAddress(u8g, dev, 0); /* instruction mode */
u8g_WriteByte(u8g, dev, 0x081);
u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
u8g_SetChipSelect(u8g, dev, 0);
return 1;
case U8G_DEV_MSG_SLEEP_ON:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_c12864_sleep_on);
return 1;
case U8G_DEV_MSG_SLEEP_OFF:
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_c12864_sleep_off);
return 1;
}
return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
}
U8G_PB_DEV(u8g_dev_st7565_nhd_c12864_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_nhd_c12864_fn, U8G_COM_SW_SPI);
U8G_PB_DEV(u8g_dev_st7565_nhd_c12864_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_nhd_c12864_fn, U8G_COM_HW_SPI);
uint8_t u8g_dev_st7565_nhd_c12864_2x_buf[WIDTH*2] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_st7565_nhd_c12864_2x_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_st7565_nhd_c12864_2x_buf};
u8g_dev_t u8g_dev_st7565_nhd_c12864_2x_sw_spi = { u8g_dev_st7565_nhd_c12864_2x_fn, &u8g_dev_st7565_nhd_c12864_2x_pb, U8G_COM_SW_SPI };
u8g_dev_t u8g_dev_st7565_nhd_c12864_2x_hw_spi = { u8g_dev_st7565_nhd_c12864_2x_fn, &u8g_dev_st7565_nhd_c12864_2x_pb, U8G_COM_HW_SPI };
/*
u8g_dev_st7687_c144mvgd.c (1.44" TFT)
Status: Started, but not finished
Universal 8bit Graphics Library
Copyright (c) 2012, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 128
#define PAGE_HEIGHT 8
#ifdef FIRST_VERSION
/*
see also: read.pudn.com/downloads115/sourcecode/app/484503/LCM_Display.c__.htm
http://en.pudn.com/downloads115/sourcecode/app/detail484503_en.html
*/
static const uint8_t u8g_dev_st7687_c144mvgd_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
0x001, /* A0=0, SW reset */
U8G_ESC_DLY(200), /* delay 200 ms */
0x0d7, /* EEPROM data auto re-load control */
U8G_ESC_ADR(1), /* data mode */
0x09f, /* ARD = 1 */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0e0, /* EEPROM control in */
U8G_ESC_ADR(1), /* data mode */
0x000, /* */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_DLY(100), /* delay 100 ms */
#ifdef NOT_REQUIRED
0x0fa, /* EEPROM function selection 8.1.66 */
U8G_ESC_ADR(1), /* data mode */
0x000, /* */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_DLY(100), /* delay 100 ms */
#endif
0x0e3, /* Read from EEPROM, 8.1.55 */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0e1, /* EEPROM control out, 8.1.53 */
U8G_ESC_DLY(100), /* delay 100 ms */
//0x028, /* display off */
0x011, /* Sleep out & booster on */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0c0, /* Vop setting, 8.1.42 */
U8G_ESC_ADR(1), /* data mode */
0x000, /* */
0x001, /* 3.6 + 256*0.04 = 13.84 Volt */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_DLY(100), /* delay 100 ms */
0x0c3, /* Bias selection, 8.1.45 */
U8G_ESC_ADR(1), /* data mode */
0x003,
U8G_ESC_ADR(0), /* instruction mode */
0x0c4, /* Booster setting 8.1.46 */
U8G_ESC_ADR(1), /* data mode */
0x007,
U8G_ESC_ADR(0), /* instruction mode */
0x0c5, /* ??? */
U8G_ESC_ADR(1), /* data mode */
0x001,
U8G_ESC_ADR(0), /* instruction mode */
0x0cb, /* FV3 with Booster x2 control, 8.1.47 */
U8G_ESC_ADR(1), /* data mode */
0x001,
U8G_ESC_ADR(0), /* instruction mode */
0x036, /* Memory data access control, 8.1.28 */
U8G_ESC_ADR(1), /* data mode */
0x080,
U8G_ESC_ADR(0), /* instruction mode */
0x0b5, /* N-line control, 8.1.37 */
U8G_ESC_ADR(1), /* data mode */
0x089,
U8G_ESC_ADR(0), /* instruction mode */
0x0d0, /* Analog circuit setting, 8.1.49 */
U8G_ESC_ADR(1), /* data mode */
0x01d,
U8G_ESC_ADR(0), /* instruction mode */
0x0b7, /* Com/Seg Scan Direction, 8.1.38 */
U8G_ESC_ADR(1), /* data mode */
0x040,
U8G_ESC_ADR(0), /* instruction mode */
0x025, /* Write contrast, 8.1.17 */
U8G_ESC_ADR(1), /* data mode */
0x03f,
U8G_ESC_ADR(0), /* instruction mode */
0x03a, /* Interface pixel format, 8.1.32 */
U8G_ESC_ADR(1), /* data mode */
0x004, /* 3: 12 bit per pixel Type A, 4: 12 bit Type B, 5: 16bit per pixel */
U8G_ESC_ADR(0), /* instruction mode */
0x0b0, /* Display Duty setting, 8.1.34 */
U8G_ESC_ADR(1), /* data mode */
0x07f,
U8G_ESC_ADR(0), /* instruction mode */
0x0f0, /* Frame Freq. in Temp range A,B,C and D, 8.1.59 */
U8G_ESC_ADR(1), /* data mode */
0x007,
0x00c,
0x00c,
0x015,
U8G_ESC_ADR(0), /* instruction mode */
0x0f9, /* Frame RGB Value, 8.1.65 */
U8G_ESC_ADR(1), /* data mode */
0x000,
0x005,
0x008,
0x00a,
0x00c,
0x00e,
0x010,
0x011,
0x012,
0x013,
0x014,
0x015,
0x016,
0x018,
0x01a,
0x01b,
U8G_ESC_ADR(0), /* instruction mode */
0x0f9, /* Frame RGB Value, 8.1.65 */
U8G_ESC_ADR(1), /* data mode */
0x000,
0x000,
0x000,
0x000,
0x033,
0x055,
0x055,
0x055,
U8G_ESC_ADR(0), /* instruction mode */
0x029, /* display on */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
#else
/*
http://www.waitingforfriday.com/images/e/e3/FTM144D01N_test.zip
*/
static const uint8_t u8g_dev_st7687_c144mvgd_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
0x011, /* Sleep out & booster on */
U8G_ESC_DLY(5), /* delay 5 ms */
0x03a, /* Interface pixel format, 8.1.32 */
U8G_ESC_ADR(1), /* data mode */
0x004, /* 3: 12 bit per pixel Type A, 4: 12 bit Type B, 5: 16bit per pixel */
U8G_ESC_ADR(0), /* instruction mode */
0x026, /* SET_GAMMA_CURVE */
U8G_ESC_ADR(1), /* data mode */
0x004,
U8G_ESC_ADR(0), /* instruction mode */
0x0f2, /* GAM_R_SEL */
U8G_ESC_ADR(1), /* data mode */
0x001, /* enable gamma adj */
U8G_ESC_ADR(0), /* instruction mode */
0x0e0, /* POSITIVE_GAMMA_CORRECT */
U8G_ESC_ADR(1), /* data mode */
0x3f,
0x25,
0x1c,
0x1e,
0x20,
0x12,
0x2a,
0x90,
0x24,
0x11,
0x00,
0x00,
0x00,
0x00,
0x00,
U8G_ESC_ADR(0), /* instruction mode */
0x0e1, /* NEGATIVE_GAMMA_CORRECT */
U8G_ESC_ADR(1), /* data mode */
0x20,
0x20,
0x20,
0x20,
0x05,
0x00,
0x15,
0xa7,
0x3d,
0x18,
0x25,
0x2a,
0x2b,
0x2b,
0x3a,
U8G_ESC_ADR(0), /* instruction mode */
0x0b1, /* FRAME_RATE_CONTROL1 */
U8G_ESC_ADR(1), /* data mode */
0x008, /* DIVA = 8 */
0x008, /* VPA = 8 */
U8G_ESC_ADR(0), /* instruction mode */
0x0b4, /* DISPLAY_INVERSION */
U8G_ESC_ADR(1), /* data mode */
0x007, /* NLA = 1, NLB = 1, NLC = 1 (all on Frame Inversion) */
U8G_ESC_ADR(0), /* instruction mode */
0x0c0, /* POWER_CONTROL1 */
U8G_ESC_ADR(1), /* data mode */
0x00a, /* VRH = 10: GVDD = 4.30 */
0x002, /* VC = 2: VCI1 = 2.65 */
U8G_ESC_ADR(0), /* instruction mode */
0x0c1, /* POWER_CONTROL2 */
U8G_ESC_ADR(1), /* data mode */
0x002, /* BT = 2: AVDD = 2xVCI1, VCL = -1xVCI1, VGH = 5xVCI1, VGL = -2xVCI1 */
U8G_ESC_ADR(0), /* instruction mode */
0x0c5, /* VCOM_CONTROL1 */
U8G_ESC_ADR(1), /* data mode */
0x050, /* VMH = 80: VCOMH voltage = 4.5 */
0x05b, /* VML = 91: VCOML voltage = -0.225 */
U8G_ESC_ADR(0), /* instruction mode */
0x0c7, /* VCOM_OFFSET_CONTROL */
U8G_ESC_ADR(1), /* data mode */
0x040, /* nVM = 0, VMF = 64: VCOMH output = VMH, VCOML output = VML */
U8G_ESC_ADR(0), /* instruction mode */
0x02a, /* SET_COLUMN_ADDRESS */
U8G_ESC_ADR(1), /* data mode */
0x000, /* */
0x000, /* */
0x000, /* */
0x07f, /* */
U8G_ESC_ADR(0), /* instruction mode */
0x02b, /* SET_PAGE_ADDRESS */
U8G_ESC_ADR(1), /* data mode */
0x000, /* */
0x000, /* */
0x000, /* */
0x07f, /* */
U8G_ESC_ADR(0), /* instruction mode */
0x036, /* SET_ADDRESS_MODE */
U8G_ESC_ADR(1), /* data mode */
0x000, /* Select display orientation */
U8G_ESC_ADR(0), /* instruction mode */
0x029, /* display on */
0x02c, /* write start */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
#endif
/* calculate bytes for Type B 4096 color display */
static uint8_t get_byte_1(uint8_t v)
{
v >>= 4;
v &= 0x0e;
return v;
}
static uint8_t get_byte_2(uint8_t v)
{
uint8_t w;
w = v;
w &= 3;
w = (w<<2) | w;
v <<= 3;
v &= 0x0e0;
w |= v;
return w;
}
uint8_t u8g_dev_st7687_c144mvgd_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7687_c144mvgd_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t y, i, j;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_SetChipSelect(u8g, dev, 1);
y = pb->p.page_y0;
ptr = pb->buf;
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_WriteByte(u8g, dev, 0x02a ); /* Column address set 8.1.20 */
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteByte(u8g, dev, 0x000 ); /* x0 */
u8g_WriteByte(u8g, dev, WIDTH-1 ); /* x1 */
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_WriteByte(u8g, dev, 0x02b ); /* Row address set 8.1.21 */
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteByte(u8g, dev, y ); /* y0 */
u8g_WriteByte(u8g, dev, y+PAGE_HEIGHT-1 ); /* y1 */
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_WriteByte(u8g, dev, 0x02c ); /* Memory write 8.1.22 */
u8g_SetAddress(u8g, dev, 1); /* data mode */
for( i = 0; i < PAGE_HEIGHT; i ++ )
{
for( j = 0; j < WIDTH; j ++ )
{
u8g_WriteByte(u8g, dev, get_byte_1(*ptr) );
u8g_WriteByte(u8g, dev, get_byte_2(*ptr) );
ptr++;
}
}
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_SetChipSelect(u8g, dev, 0);
}
break;
}
return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_st7687_c144mvgd_8h8_buf[WIDTH*8] U8G_NOCOMMON ;
u8g_pb_t u8g_st7687_c144mvgd_8h8_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_st7687_c144mvgd_8h8_buf};
u8g_dev_t u8g_dev_st7687_c144mvgd_sw_spi = { u8g_dev_st7687_c144mvgd_fn, &u8g_st7687_c144mvgd_8h8_pb, u8g_com_arduino_sw_spi_fn };
u8g_dev_t u8g_dev_st7687_c144mvgd_8bit = { u8g_dev_st7687_c144mvgd_fn, &u8g_st7687_c144mvgd_8h8_pb, U8G_COM_PARALLEL };
/*
u8g_dev_st7920_128x64.c
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 64
#define PAGE_HEIGHT 8
/* init sequence from https://github.com/adafruit/ST7565-LCD/blob/master/ST7565/ST7565.cpp */
static const uint8_t u8g_dev_st7920_128x64_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
U8G_ESC_DLY(100), /* 8 Dez 2012: additional delay 100 ms because of reset*/
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_DLY(50), /* delay 50 ms */
0x038, /* 8 Bit interface (DL=1), basic instruction set (RE=0) */
0x00c, /* display on, cursor & blink off; 0x08: all off */
0x006, /* Entry mode: Cursor move to right ,DDRAM address counter (AC) plus 1, no shift */
0x002, /* disable scroll, enable CGRAM adress */
0x001, /* clear RAM, needs 1.6 ms */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
uint8_t u8g_dev_st7920_128x64_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7920_128x64_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t y, i;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_SetChipSelect(u8g, dev, 1);
y = pb->p.page_y0;
ptr = pb->buf;
for( i = 0; i < 8; i ++ )
{
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_WriteByte(u8g, dev, 0x03e ); /* enable extended mode */
if ( y < 32 )
{
u8g_WriteByte(u8g, dev, 0x080 | y ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 ); /* set x pos to 0*/
}
else
{
u8g_WriteByte(u8g, dev, 0x080 | (y-32) ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 | 8); /* set x pos to 64*/
}
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, WIDTH/8, ptr);
ptr += WIDTH/8;
y++;
}
u8g_SetChipSelect(u8g, dev, 0);
}
break;
}
return u8g_dev_pb8h1_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_st7920_128x64_4x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7920_128x64_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t y, i;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_SetChipSelect(u8g, dev, 1);
y = pb->p.page_y0;
ptr = pb->buf;
for( i = 0; i < 32; i ++ )
{
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_WriteByte(u8g, dev, 0x03e ); /* enable extended mode */
if ( y < 32 )
{
u8g_WriteByte(u8g, dev, 0x080 | y ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 ); /* set x pos to 0*/
}
else
{
u8g_WriteByte(u8g, dev, 0x080 | (y-32) ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 | 8); /* set x pos to 64*/
}
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, WIDTH/8, ptr);
ptr += WIDTH/8;
y++;
}
u8g_SetChipSelect(u8g, dev, 0);
}
break;
}
return u8g_dev_pb32h1_base_fn(u8g, dev, msg, arg);
}
U8G_PB_DEV(u8g_dev_st7920_128x64_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7920_128x64_fn, U8G_COM_ST7920_SW_SPI);
U8G_PB_DEV(u8g_dev_st7920_128x64_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7920_128x64_fn, U8G_COM_ST7920_HW_SPI);
U8G_PB_DEV(u8g_dev_st7920_128x64_8bit, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7920_128x64_fn, U8G_COM_FAST_PARALLEL);
U8G_PB_DEV(u8g_dev_st7920_128x64_custom, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7920_128x64_fn, u8g_com_arduino_st7920_custom_fn);
#define QWIDTH (WIDTH*4)
uint8_t u8g_dev_st7920_128x64_4x_buf[QWIDTH] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_st7920_128x64_4x_pb = { {32, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_st7920_128x64_4x_buf};
u8g_dev_t u8g_dev_st7920_128x64_4x_sw_spi = { u8g_dev_st7920_128x64_4x_fn, &u8g_dev_st7920_128x64_4x_pb, U8G_COM_ST7920_SW_SPI };
u8g_dev_t u8g_dev_st7920_128x64_4x_hw_spi = { u8g_dev_st7920_128x64_4x_fn, &u8g_dev_st7920_128x64_4x_pb, U8G_COM_ST7920_HW_SPI };
u8g_dev_t u8g_dev_st7920_128x64_4x_8bit = { u8g_dev_st7920_128x64_4x_fn, &u8g_dev_st7920_128x64_4x_pb, U8G_COM_FAST_PARALLEL };
u8g_dev_t u8g_dev_st7920_128x64_4x_custom = { u8g_dev_st7920_128x64_4x_fn, &u8g_dev_st7920_128x64_4x_pb, u8g_com_arduino_st7920_custom_fn };
/*
u8g_dev_st7920_192x32.c
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 192
#define HEIGHT 32
/* init sequence from https://github.com/adafruit/ST7565-LCD/blob/master/ST7565/ST7565.cpp */
static const uint8_t u8g_dev_st7920_192x32_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
U8G_ESC_DLY(100), /* 8 Dez 2012: additional delay 100 ms because of reset*/
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_DLY(50), /* delay 50 ms */
0x038, /* 8 Bit interface (DL=1), basic instruction set (RE=0) */
0x00c, /* display on, cursor & blink off; 0x08: all off */
0x006, /* Entry mode: Cursor move to right ,DDRAM address counter (AC) plus 1, no shift */
0x002, /* disable scroll, enable CGRAM adress */
0x001, /* clear RAM, needs 1.6 ms */
U8G_ESC_DLY(100), /* delay 10 ms */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
uint8_t u8g_dev_st7920_192x32_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7920_192x32_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t y, i;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_SetChipSelect(u8g, dev, 1);
y = pb->p.page_y0;
ptr = pb->buf;
for( i = 0; i < 8; i ++ )
{
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_WriteByte(u8g, dev, 0x03e ); /* enable extended mode */
u8g_WriteByte(u8g, dev, 0x080 | y ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 ); /* set x pos to 0*/
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, WIDTH/8, ptr);
ptr += WIDTH/8;
y++;
}
u8g_SetChipSelect(u8g, dev, 0);
}
break;
}
return u8g_dev_pb8h1_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_st7920_192x32_4x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7920_192x32_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t y, i;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_SetChipSelect(u8g, dev, 1);
y = pb->p.page_y0;
ptr = pb->buf;
for( i = 0; i < 32; i ++ )
{
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_WriteByte(u8g, dev, 0x03e ); /* enable extended mode */
u8g_WriteByte(u8g, dev, 0x080 | y ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 ); /* set x pos to 0*/
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, WIDTH/8, ptr);
ptr += WIDTH/8;
y++;
}
u8g_SetChipSelect(u8g, dev, 0);
}
break;
}
return u8g_dev_pb32h1_base_fn(u8g, dev, msg, arg);
}
U8G_PB_DEV(u8g_dev_st7920_192x32_sw_spi, WIDTH, HEIGHT, 8, u8g_dev_st7920_192x32_fn, U8G_COM_ST7920_SW_SPI);
U8G_PB_DEV(u8g_dev_st7920_192x32_hw_spi, WIDTH, HEIGHT, 8, u8g_dev_st7920_192x32_fn, U8G_COM_ST7920_HW_SPI);
U8G_PB_DEV(u8g_dev_st7920_192x32_8bit, WIDTH, HEIGHT, 8, u8g_dev_st7920_192x32_fn, U8G_COM_FAST_PARALLEL);
#define QWIDTH (WIDTH*4)
uint8_t u8g_dev_st7920_192x32_4x_buf[QWIDTH] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_st7920_192x32_4x_pb = { {32, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_st7920_192x32_4x_buf};
u8g_dev_t u8g_dev_st7920_192x32_4x_sw_spi = { u8g_dev_st7920_192x32_4x_fn, &u8g_dev_st7920_192x32_4x_pb, U8G_COM_ST7920_SW_SPI };
u8g_dev_t u8g_dev_st7920_192x32_4x_hw_spi = { u8g_dev_st7920_192x32_4x_fn, &u8g_dev_st7920_192x32_4x_pb, U8G_COM_ST7920_HW_SPI };
u8g_dev_t u8g_dev_st7920_192x32_4x_8bit = { u8g_dev_st7920_192x32_4x_fn, &u8g_dev_st7920_192x32_4x_pb, U8G_COM_FAST_PARALLEL };
/*
u8g_dev_st7920_202x32.c
tested with CFAG20232
Universal 8bit Graphics Library
Copyright (c) 2011, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "u8g.h"
#define WIDTH 202
#define HEIGHT 32
#define PAGE_HEIGHT 8
/* init sequence from https://github.com/adafruit/ST7565-LCD/blob/master/ST7565/ST7565.cpp */
static const uint8_t u8g_dev_st7920_202x32_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* instruction mode */
U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
U8G_ESC_DLY(100), /* 8 Dez 2012: additional delay 100 ms because of reset*/
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_DLY(50), /* delay 50 ms */
0x038, /* 8 Bit interface (DL=1), basic instruction set (RE=0) */
0x00c, /* display on, cursor & blink off; 0x08: all off */
0x006, /* Entry mode: Cursor move to right ,DDRAM address counter (AC) plus 1, no shift */
0x002, /* disable scroll, enable CGRAM adress */
0x001, /* clear RAM, needs 1.6 ms */
U8G_ESC_DLY(100), /* delay 10 ms */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
uint8_t u8g_dev_st7920_202x32_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7920_202x32_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t y, i;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_SetChipSelect(u8g, dev, 1);
y = pb->p.page_y0;
ptr = pb->buf;
for( i = 0; i < 8; i ++ )
{
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_WriteByte(u8g, dev, 0x03e ); /* enable extended mode */
u8g_WriteByte(u8g, dev, 0x080 | y ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 ); /* set x pos to 0*/
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, WIDTH/8, ptr);
ptr += WIDTH/8;
y++;
}
u8g_SetChipSelect(u8g, dev, 0);
}
break;
}
return u8g_dev_pb8h1_base_fn(u8g, dev, msg, arg);
}
uint8_t u8g_dev_st7920_202x32_4x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7920_202x32_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t y, i;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_SetChipSelect(u8g, dev, 1);
y = pb->p.page_y0;
ptr = pb->buf;
for( i = 0; i < 32; i ++ )
{
u8g_SetAddress(u8g, dev, 0); /* cmd mode */
u8g_WriteByte(u8g, dev, 0x03e ); /* enable extended mode */
u8g_WriteByte(u8g, dev, 0x080 | y ); /* y pos */
u8g_WriteByte(u8g, dev, 0x080 ); /* set x pos to 0*/
u8g_SetAddress(u8g, dev, 1); /* data mode */
u8g_WriteSequence(u8g, dev, WIDTH/8, ptr);
ptr += WIDTH/8;
y++;
}
u8g_SetChipSelect(u8g, dev, 0);
}
break;
}
return u8g_dev_pb32h1_base_fn(u8g, dev, msg, arg);
}
U8G_PB_DEV(u8g_dev_st7920_202x32_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7920_202x32_fn, U8G_COM_ST7920_SW_SPI);
U8G_PB_DEV(u8g_dev_st7920_202x32_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7920_202x32_fn, U8G_COM_ST7920_HW_SPI);
U8G_PB_DEV(u8g_dev_st7920_202x32_8bit, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7920_202x32_fn, U8G_COM_FAST_PARALLEL);
#define QWIDTH (WIDTH*4)
uint8_t u8g_dev_st7920_202x32_4x_buf[QWIDTH] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_st7920_202x32_4x_pb = { {32, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_st7920_202x32_4x_buf};
u8g_dev_t u8g_dev_st7920_202x32_4x_sw_spi = { u8g_dev_st7920_202x32_4x_fn, &u8g_dev_st7920_202x32_4x_pb, U8G_COM_ST7920_SW_SPI };
u8g_dev_t u8g_dev_st7920_202x32_4x_hw_spi = { u8g_dev_st7920_202x32_4x_fn, &u8g_dev_st7920_202x32_4x_pb, U8G_COM_ST7920_HW_SPI };
u8g_dev_t u8g_dev_st7920_202x32_4x_8bit = { u8g_dev_st7920_202x32_4x_fn, &u8g_dev_st7920_202x32_4x_pb, U8G_COM_FAST_PARALLEL };
/*
u8g_dev_t6963_128x128.c
Universal 8bit Graphics Library
Copyright (c) 2013, olikraus@gmail.com
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or other
materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Application Notes for the MGLS 128x128
www.baso.no/content/pdf/T6963C_Application.pdf
Hitachi App Notes:
https://www.sparkfun.com/datasheets/LCD/Monochrome/AN-029-Toshiba_T6963C.pdf
Notes:
The font selection pins should generate the 8x8 font.
For the MGLS240128TZ only FS1 is available on pin 18.
FS1 must be low to generate the 8x8 font.
*/
#include "u8g.h"
#define WIDTH 128
#define HEIGHT 128
#define PAGE_HEIGHT 16
/*
http://www.mark-products.com/graphics.htm#240x64%20Pixel%20Format
*/
/* text is not used, so settings are not relevant */
static const uint8_t u8g_dev_t6963_128x128_init_seq[] PROGMEM = {
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_ADR(0), /* data mode */
U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
U8G_ESC_CS(1), /* enable chip */
U8G_ESC_DLY(50), /* delay 50 ms */
U8G_ESC_ADR(0), /* data mode */
0x000, /* low byte */
0x000, /* height byte */
U8G_ESC_ADR(1), /* instruction mode */
0x021, /* set cursor position */
U8G_ESC_ADR(0), /* data mode */
0x000, /* low byte */
0x000, /* height byte */
U8G_ESC_ADR(1), /* instruction mode */
0x022, /* set offset */
U8G_ESC_ADR(0), /* data mode */
0x000, /* low byte */
0x000, /* height byte */
U8G_ESC_ADR(1), /* instruction mode */
0x040, /* text home */
U8G_ESC_ADR(0), /* data mode */
WIDTH/8, /* low byte */
0x000, /* height byte */
U8G_ESC_ADR(1), /* instruction mode */
0x041, /* text columns */
U8G_ESC_ADR(0), /* data mode */
0x000, /* low byte */
0x000, /* height byte */
U8G_ESC_ADR(1), /* instruction mode */
0x042, /* graphics home */
U8G_ESC_ADR(0), /* data mode */
WIDTH/8, /* low byte */
0x000, /* height byte */
U8G_ESC_ADR(1), /* instruction mode */
0x043, /* graphics columns */
// mode set
// 0x080: Internal CG, OR Mode
// 0x081: Internal CG, EXOR Mode
// 0x083: Internal CG, AND Mode
// 0x088: External CG, OR Mode
// 0x089: External CG, EXOR Mode
// 0x08B: External CG, AND Mode
U8G_ESC_ADR(1), /* instruction mode */
0x080, /* mode register: OR Mode, Internal Character Mode */
U8G_ESC_ADR(1), /* instruction mode */
// display mode
// 0x090: Display off
// 0x094: Graphic off, text on, cursor off, blink off
// 0x096: Graphic off, text on, cursor on, blink off
// 0x097: Graphic off, text on, cursor on, blink on
// 0x098: Graphic on, text off, cursor off, blink off
// 0x09a: Graphic on, text off, cursor on, blink off
// ...
// 0x09c: Graphic on, text on, cursor off, blink off
// 0x09f: Graphic on, text on, cursor on, blink on
0x098, /* mode register: Display Mode, Graphics on, Text off, Cursor off */
U8G_ESC_ADR(0), /* data mode */
0x000, /* low byte */
0x000, /* height byte */
U8G_ESC_ADR(1), /* instruction mode */
0x024, /* set adr pointer */
U8G_ESC_DLY(100), /* delay 100 ms */
U8G_ESC_ADR(0), /* data mode */
U8G_ESC_CS(0), /* disable chip */
U8G_ESC_END /* end of sequence */
};
uint8_t u8g_dev_t6963_128x128_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
{
switch(msg)
{
case U8G_DEV_MSG_INIT:
u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_NONE);
u8g_WriteEscSeqP(u8g, dev, u8g_dev_t6963_128x128_init_seq);
break;
case U8G_DEV_MSG_STOP:
break;
case U8G_DEV_MSG_PAGE_NEXT:
{
uint8_t y, i;
uint16_t disp_ram_adr;
uint8_t *ptr;
u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
u8g_SetAddress(u8g, dev, 0); /* data mode */
u8g_SetChipSelect(u8g, dev, 1);
y = pb->p.page_y0;
ptr = pb->buf;
disp_ram_adr = WIDTH/8;
disp_ram_adr *= y;
for( i = 0; i < PAGE_HEIGHT; i ++ )
{
u8g_SetAddress(u8g, dev, 0); /* data mode */
u8g_WriteByte(u8g, dev, disp_ram_adr&255 ); /* address low byte */
u8g_WriteByte(u8g, dev, disp_ram_adr>>8 ); /* address hight byte */
u8g_SetAddress(u8g, dev, 1); /* cmd mode */
u8g_WriteByte(u8g, dev, 0x024 ); /* set adr ptr */
u8g_WriteSequence(u8g, dev, WIDTH/8, ptr);
ptr += WIDTH/8;
disp_ram_adr += WIDTH/8;
}
u8g_SetAddress(u8g, dev, 0); /* data mode */
u8g_SetChipSelect(u8g, dev, 0);
}
break;
}
return u8g_dev_pb16h1_base_fn(u8g, dev, msg, arg);
}
// U8G_PB_DEV(u8g_dev_t6963_128x128_8bit, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_t6963_128x128_fn, U8G_COM_T6963);
uint8_t u8g_dev_t6963_128x128_2x_bw_buf[WIDTH/8*PAGE_HEIGHT] U8G_NOCOMMON ;
u8g_pb_t u8g_dev_t6963_128x128_2x_bw_pb = { {PAGE_HEIGHT, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_t6963_128x128_2x_bw_buf};
u8g_dev_t u8g_dev_t6963_128x128_8bit = { u8g_dev_t6963_128x128_fn, &u8g_dev_t6963_128x128_2x_bw_pb, U8G_COM_T6963 };
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