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ruanhaishen
Nodemcu Firmware
Commits
9a30797b
Commit
9a30797b
authored
Nov 17, 2016
by
Mike Pye
Committed by
Marcel Stör
Nov 17, 2016
Browse files
Add note on dev board usage of SPI bus 0 (#1591)
parent
1d0cf5e8
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docs/en/modules/spi.md
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@@ -6,6 +6,16 @@
All transactions for sending and receiving are most-significant-bit first and least-significant last.
For technical details of the underlying hardware refer to
[
metalphreak's ESP8266 HSPI articles
](
http://d.av.id.au/blog/tag/hspi/
)
.
## A note on the SPI busses
The ESP hardware provides two SPI busses, with IDs 0, and 1, which map to pins
generally labelled SPI and HSPI.
If you are using any kind of development board which provides flash, then bus
ID 0 (SPI) is almost certainly used for communicating with the flash chip.
You probably want to choose bus ID 1 (HSPI) for your communication, as you
will have uncontended use of it.
## High Level Functions
The high level functions provide a send & receive API for half- and
full-duplex mode. Sent and received data items are restricted to 1 - 32 bit
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