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ruanhaishen
Nodemcu Firmware
Commits
bf74b617
Commit
bf74b617
authored
Jan 13, 2016
by
jfollas
Browse files
SPI: Implemented CPOL=1
Reference:
http://bbs.espressif.com/viewtopic.php?f=49&t=1570
parent
7d3202e8
Changes
3
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Inline
Side-by-side
app/driver/spi.c
View file @
bf74b617
...
...
@@ -87,14 +87,12 @@ void spi_master_init(uint8 spi_no, unsigned cpol, unsigned cpha, uint32_t clock_
SET_PERI_REG_MASK
(
SPI_USER
(
spi_no
),
SPI_CS_SETUP
|
SPI_CS_HOLD
|
SPI_RD_BYTE_ORDER
|
SPI_WR_BYTE_ORDER
|
SPI_DOUTDIN
);
//set clock polarity
// TODO: This doesn't work
//if (cpol == 1) {
// SET_PERI_REG_MASK(SPI_CTRL2(spi_no), (SPI_CK_OUT_HIGH_MODE<<SPI_CK_OUT_HIGH_MODE_S));
//} else {
// SET_PERI_REG_MASK(SPI_CTRL2(spi_no), (SPI_CK_OUT_LOW_MODE<<SPI_CK_OUT_LOW_MODE_S));
//}
//os_printf("SPI_CTRL2 is %08x\n",READ_PERI_REG(SPI_CTRL2(spi_no)));
//set clock polarity (Reference: http://bbs.espressif.com/viewtopic.php?f=49&t=1570)
if
(
cpol
==
1
)
{
SET_PERI_REG_MASK
(
SPI_PIN
(
spi_no
),
SPI_IDLE_EDGE
);
}
else
{
CLEAR_PERI_REG_MASK
(
SPI_PIN
(
spi_no
),
SPI_IDLE_EDGE
);
}
//set clock phase
if
(
cpha
==
1
)
{
...
...
app/include/driver/spi_register.h
View file @
bf74b617
...
...
@@ -102,6 +102,7 @@
#define SPI_CS2_DIS (BIT(2))
#define SPI_CS1_DIS (BIT(1))
#define SPI_CS0_DIS (BIT(0))
#define SPI_IDLE_EDGE (BIT(29))
#define SPI_SLAVE(i) (REG_SPI_BASE(i) + 0x30)
#define SPI_SYNC_RESET (BIT(31))
...
...
app/modules/spi.c
View file @
bf74b617
...
...
@@ -30,10 +30,6 @@ static int spi_setup( lua_State *L )
if
(
cpol
!=
PLATFORM_SPI_CPOL_LOW
&&
cpol
!=
PLATFORM_SPI_CPOL_HIGH
)
{
return
luaL_error
(
L
,
"wrong arg type"
);
}
// CPOL_HIGH is not implemented, see app/driver/spi.c spi_master_init()
if
(
cpol
==
PLATFORM_SPI_CPOL_HIGH
)
{
return
luaL_error
(
L
,
"cpol=high is not implemented"
);
}
if
(
cpha
!=
PLATFORM_SPI_CPHA_LOW
&&
cpha
!=
PLATFORM_SPI_CPHA_HIGH
)
{
return
luaL_error
(
L
,
"wrong arg type"
);
...
...
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